mirror of
https://github.com/torvalds/linux.git
synced 2026-04-18 06:44:00 -04:00
af74daf916
Add AMD Zen5 support for address translation. Zen5 systems may be configured to use 'Normalized addresses'. Then, host physical addresses (HPA) are different from their system physical addresses (SPA). The endpoint has its own physical address space and an incoming HPA is already converted to the device's physical address (DPA). Thus it has interleaving disabled and CXL endpoints are programmed passthrough (DPA == HPA). Host Physical Addresses (HPAs) need to be translated from the endpoint to its CXL host bridge, esp. to identify the endpoint's root decoder and region's address range. ACPI Platform Runtime Mechanism (PRM) provides a handler to translate the DPA to its SPA. This is documented in: AMD Family 1Ah Models 00h–0Fh and Models 10h–1Fh ACPI v6.5 Porting Guide, Publication # 58088 https://www.amd.com/en/search/documentation/hub.html With Normalized Addressing this PRM handler must be used to translate an HPA of an endpoint to its SPA. Do the following to implement AMD Zen5 address translation: Introduce a new file core/atl.c to handle ACPI PRM specific address translation code. Naming is loosely related to the kernel's AMD Address Translation Library (CONFIG_AMD_ATL) but implementation does not depend on it, nor it is vendor specific. Use Kbuild and Kconfig options respectively to enable the code depending on architecture and platform options. AMD Zen5 systems support the ACPI PRM CXL Address Translation firmware call (see ACPI v6.5 Porting Guide, Address Translation - CXL DPA to System Physical Address). Firmware enables the PRM handler if the platform has address translation implemented. Check firmware and kernel support of ACPI PRM using the specific GUID. On success enable address translation by setting up the earlier introduced root port callback, see function cxl_prm_setup_translation(). Setup is done in cxl_setup_prm_address_translation(), it is the only function that needs to be exported. For low level PRM firmware calls, use the ACPI framework. Identify the region's interleaving ways by inspecting the address ranges. Also determine the interleaving granularity using the address translation callback. Note that the position of the chunk from one interleaving block to the next may vary and thus cannot be considered constant. Address offsets larger than the interleaving block size cannot be used to calculate the granularity. Thus, probe the granularity using address translation for various HPAs in the same interleaving block. [ dj: Add atl.o build to cxl_test ] Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Tested-by: Gregory Price <gourry@gourry.net> Signed-off-by: Robert Richter <rrichter@amd.com> Link: https://patch.msgid.link/20260114164837.1076338-11-rrichter@amd.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
74 lines
2.2 KiB
Makefile
74 lines
2.2 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0
|
|
ldflags-y += --wrap=acpi_table_parse_cedt
|
|
ldflags-y += --wrap=is_acpi_device_node
|
|
ldflags-y += --wrap=acpi_evaluate_integer
|
|
ldflags-y += --wrap=acpi_pci_find_root
|
|
ldflags-y += --wrap=nvdimm_bus_register
|
|
ldflags-y += --wrap=cxl_await_media_ready
|
|
ldflags-y += --wrap=devm_cxl_add_rch_dport
|
|
ldflags-y += --wrap=cxl_endpoint_parse_cdat
|
|
ldflags-y += --wrap=cxl_dport_init_ras_reporting
|
|
ldflags-y += --wrap=devm_cxl_endpoint_decoders_setup
|
|
ldflags-y += --wrap=hmat_get_extended_linear_cache_size
|
|
|
|
DRIVERS := ../../../drivers
|
|
CXL_SRC := $(DRIVERS)/cxl
|
|
CXL_CORE_SRC := $(DRIVERS)/cxl/core
|
|
ccflags-y := -I$(srctree)/drivers/cxl/
|
|
ccflags-y += -D__mock=__weak
|
|
ccflags-y += -DCXL_TEST_ENABLE=1
|
|
ccflags-y += -DTRACE_INCLUDE_PATH=$(CXL_CORE_SRC) -I$(srctree)/drivers/cxl/core/
|
|
|
|
obj-m += cxl_acpi.o
|
|
|
|
cxl_acpi-y := $(CXL_SRC)/acpi.o
|
|
cxl_acpi-y += mock_acpi.o
|
|
cxl_acpi-y += config_check.o
|
|
cxl_acpi-y += cxl_acpi_test.o
|
|
|
|
obj-m += cxl_pmem.o
|
|
|
|
cxl_pmem-y := $(CXL_SRC)/pmem.o
|
|
cxl_pmem-y += $(CXL_SRC)/security.o
|
|
cxl_pmem-y += config_check.o
|
|
cxl_pmem-y += cxl_pmem_test.o
|
|
|
|
obj-m += cxl_port.o
|
|
|
|
cxl_port-y := $(CXL_SRC)/port.o
|
|
cxl_port-y += config_check.o
|
|
cxl_port-y += cxl_port_test.o
|
|
|
|
|
|
obj-m += cxl_mem.o
|
|
|
|
cxl_mem-y := $(CXL_SRC)/mem.o
|
|
cxl_mem-y += config_check.o
|
|
cxl_mem-y += cxl_mem_test.o
|
|
|
|
obj-m += cxl_core.o
|
|
|
|
cxl_core-y := $(CXL_CORE_SRC)/port.o
|
|
cxl_core-y += $(CXL_CORE_SRC)/pmem.o
|
|
cxl_core-y += $(CXL_CORE_SRC)/regs.o
|
|
cxl_core-y += $(CXL_CORE_SRC)/memdev.o
|
|
cxl_core-y += $(CXL_CORE_SRC)/mbox.o
|
|
cxl_core-y += $(CXL_CORE_SRC)/pci.o
|
|
cxl_core-y += $(CXL_CORE_SRC)/hdm.o
|
|
cxl_core-y += $(CXL_CORE_SRC)/pmu.o
|
|
cxl_core-y += $(CXL_CORE_SRC)/cdat.o
|
|
cxl_core-y += $(CXL_CORE_SRC)/ras.o
|
|
cxl_core-$(CONFIG_TRACING) += $(CXL_CORE_SRC)/trace.o
|
|
cxl_core-$(CONFIG_CXL_REGION) += $(CXL_CORE_SRC)/region.o
|
|
cxl_core-$(CONFIG_CXL_MCE) += $(CXL_CORE_SRC)/mce.o
|
|
cxl_core-$(CONFIG_CXL_FEATURES) += $(CXL_CORE_SRC)/features.o
|
|
cxl_core-$(CONFIG_CXL_EDAC_MEM_FEATURES) += $(CXL_CORE_SRC)/edac.o
|
|
cxl_core-$(CONFIG_CXL_ATL) += $(CXL_CORE_SRC)/atl.o
|
|
cxl_core-y += config_check.o
|
|
cxl_core-y += cxl_core_test.o
|
|
cxl_core-y += cxl_core_exports.o
|
|
|
|
KBUILD_CFLAGS := $(filter-out -Wmissing-prototypes -Wmissing-declarations, $(KBUILD_CFLAGS))
|
|
|
|
obj-m += test/
|