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Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SA8775P SoCs. The L3 instance on the SA8775P SoC is similar to those on SoCs like SM8250 and SC7280. These SoCs use the PERF register instead of L3_REG for programming the performance level, which is managed in the data associated with the target-specific compatibles. Since the hardware remains the same across all EPSS-supporting SoCs, the generic compatible is retained for all SoCs. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com> Link: https://lore.kernel.org/r/20250415095343.32125-2-quic_rlaggysh@quicinc.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
80 lines
1.8 KiB
YAML
80 lines
1.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interconnect/qcom,osm-l3.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider
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maintainers:
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- Sibi Sankar <quic_sibis@quicinc.com>
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description:
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L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM.
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The OSM L3 interconnect provider aggregates the L3 bandwidth requests
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from CPU/GPU and relays it to the OSM.
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- qcom,sc7180-osm-l3
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- qcom,sc8180x-osm-l3
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- qcom,sdm670-osm-l3
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- qcom,sdm845-osm-l3
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- qcom,sm6350-osm-l3
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- qcom,sm8150-osm-l3
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- const: qcom,osm-l3
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- items:
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- enum:
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- qcom,sa8775p-epss-l3
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- qcom,sc7280-epss-l3
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- qcom,sc8280xp-epss-l3
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- qcom,sm6375-cpucp-l3
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- qcom,sm8250-epss-l3
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- qcom,sm8350-epss-l3
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- qcom,sm8650-epss-l3
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- const: qcom,epss-l3
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reg:
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maxItems: 1
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clocks:
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items:
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- description: xo clock
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- description: alternate clock
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clock-names:
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items:
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- const: xo
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- const: alternate
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'#interconnect-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#interconnect-cells'
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additionalProperties: false
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examples:
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- |
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#define GPLL0 165
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#define RPMH_CXO_CLK 0
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osm_l3: interconnect@17d41000 {
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compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3";
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reg = <0x17d41000 0x1400>;
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
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clock-names = "xo", "alternate";
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#interconnect-cells = <1>;
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};
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