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25a2aa779f
Add support to manage power limits using pcode mailbox commands for supported platforms. v2: - Address review comments. (Badal) - Use mailbox commands instead of registers to manage power limits for BMG. - Clamp the maximum power limit to GPU firmware default value. v3: - Clamp power limit in write also for platforms with mailbox support. v4: - Remove unnecessary debug prints. (Badal) v5: - Update description of variable pl1_on_boot to fix kernel-doc error. v6: - Improve commit message, refer to BIOS as GPU firmware. - Change macro READ_PL_FROM_BIOS to READ_PL_FROM_FW. - Rectify drm_warn to drm_info. Signed-off-by: Karthik Poosa <karthik.poosa@intel.com> Fixes:e90f7a58e6("drm/xe/hwmon: Add HWMON support for BMG") Reviewed-by: Badal Nilawar <badal.nilawar@intel.com> Link: https://lore.kernel.org/r/20250529163458.2354509-2-karthik.poosa@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> (cherry picked from commit7596d839f6) Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
30 lines
950 B
C
30 lines
950 B
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2024 Intel Corporation
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*/
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#ifndef _XE_PCODE_REGS_H_
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#define _XE_PCODE_REGS_H_
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#include "regs/xe_reg_defs.h"
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/*
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* This file contains addresses of PCODE registers visible through GT MMIO space.
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*/
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#define PVC_GT0_PACKAGE_ENERGY_STATUS XE_REG(0x281004)
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#define PVC_GT0_PACKAGE_RAPL_LIMIT XE_REG(0x281008)
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#define PVC_GT0_PACKAGE_POWER_SKU_UNIT XE_REG(0x281068)
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#define PVC_GT0_PLATFORM_ENERGY_STATUS XE_REG(0x28106c)
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#define PVC_GT0_PACKAGE_POWER_SKU XE_REG(0x281080)
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#define BMG_PACKAGE_ENERGY_STATUS XE_REG(0x138120)
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#define BMG_FAN_1_SPEED XE_REG(0x138140)
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#define BMG_FAN_2_SPEED XE_REG(0x138170)
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#define BMG_FAN_3_SPEED XE_REG(0x1381a0)
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#define BMG_VRAM_TEMPERATURE XE_REG(0x1382c0)
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#define BMG_PACKAGE_TEMPERATURE XE_REG(0x138434)
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#define BMG_PLATFORM_ENERGY_STATUS XE_REG(0x138458)
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#endif /* _XE_PCODE_REGS_H_ */
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