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Recent discussions with the hardware architects have revealed that the TIMESTAMP_OVERRIDE register is never expected to hold a valid/useful value on production hardware. That register would only get used by hardware workarounds (although there are none that use it today) or during early internal hardware testing. Due to lack of documentation it's not clear exactly what the driver should be doing if CTC_MODE[0] is set (or even whether that's a setting that would ever be encountered on real hardware), but it's definitely not what Xe and i915 have been doing. So drop the incorrect code trying to use TIMESTAMP_REGISTER. If the driver does encounter CTC_MODE[0] in the wild, we'll print a warning and just continue trying to use the crystal clock frequency since that's probably less incorrect than what we're doing today. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250225224908.1671554-2-matthew.d.roper@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
62 lines
1.6 KiB
C
62 lines
1.6 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef _XE_REGS_H_
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#define _XE_REGS_H_
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#include "regs/xe_reg_defs.h"
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#define GU_CNTL_PROTECTED XE_REG(0x10100C)
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#define DRIVERINT_FLR_DIS REG_BIT(31)
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#define GU_CNTL XE_REG(0x101010)
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#define LMEM_INIT REG_BIT(7)
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#define DRIVERFLR REG_BIT(31)
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#define XEHP_CLOCK_GATE_DIS XE_REG(0x101014)
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#define SGSI_SIDECLK_DIS REG_BIT(17)
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#define GU_DEBUG XE_REG(0x101018)
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#define DRIVERFLR_STATUS REG_BIT(31)
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#define VIRTUAL_CTRL_REG XE_REG(0x10108c)
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#define GUEST_GTT_UPDATE_EN REG_BIT(8)
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#define XEHP_MTCFG_ADDR XE_REG(0x101800)
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#define TILE_COUNT REG_GENMASK(15, 8)
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#define GGC XE_REG(0x108040)
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#define GMS_MASK REG_GENMASK(15, 8)
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#define GGMS_MASK REG_GENMASK(7, 6)
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#define DSMBASE XE_REG(0x1080C0)
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#define BDSM_MASK REG_GENMASK64(63, 20)
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#define GSMBASE XE_REG(0x108100)
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#define STOLEN_RESERVED XE_REG(0x1082c0)
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#define WOPCM_SIZE_MASK REG_GENMASK64(9, 7)
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#define MTL_RP_STATE_CAP XE_REG(0x138000)
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#define MTL_GT_RPA_FREQUENCY XE_REG(0x138008)
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#define MTL_GT_RPE_FREQUENCY XE_REG(0x13800c)
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#define MTL_MEDIAP_STATE_CAP XE_REG(0x138020)
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#define MTL_RPN_CAP_MASK REG_GENMASK(24, 16)
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#define MTL_RP0_CAP_MASK REG_GENMASK(8, 0)
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#define MTL_MPA_FREQUENCY XE_REG(0x138028)
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#define MTL_RPA_MASK REG_GENMASK(8, 0)
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#define MTL_MPE_FREQUENCY XE_REG(0x13802c)
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#define MTL_RPE_MASK REG_GENMASK(8, 0)
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#define VF_CAP_REG XE_REG(0x1901f8, XE_REG_OPTION_VF)
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#define VF_CAP REG_BIT(0)
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#define PVC_RP_STATE_CAP XE_REG(0x281014)
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#endif
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