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Add support for Tegra234 P2U (PIPE to UPHY) module block which is a glue module instantiated once for each PCIe lane between Synopsys DesignWare core based PCIe IP and Universal PHY block. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220629060435.25297-2-vidyas@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
54 lines
1.4 KiB
YAML
54 lines
1.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/phy/phy-tegra194-p2u.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: NVIDIA Tegra194 & Tegra234 P2U binding
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maintainers:
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- Thierry Reding <treding@nvidia.com>
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description: >
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Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High
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Speed) each interfacing with 12 and 8 P2U instances respectively.
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Tegra234 has three PHY bricks namely HSIO, NVHS and GBE (Gigabit Ethernet)
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each interfacing with 8, 8 and 8 P2U instances respectively.
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A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE
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interface and PHY of HSIO/NVHS/GBE bricks. Each P2U instance represents one
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PCIe lane.
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properties:
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compatible:
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enum:
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- nvidia,tegra194-p2u
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- nvidia,tegra234-p2u
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reg:
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maxItems: 1
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description: Should be the physical address space and length of respective each P2U instance.
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reg-names:
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items:
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- const: ctl
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nvidia,skip-sz-protect-en:
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description: Should be present if two PCIe retimers are present between
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the root port and its immediate downstream device.
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type: boolean
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'#phy-cells':
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const: 0
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additionalProperties: false
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examples:
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- |
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p2u_hsio_0: phy@3e10000 {
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compatible = "nvidia,tegra194-p2u";
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reg = <0x03e10000 0x10000>;
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reg-names = "ctl";
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#phy-cells = <0>;
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};
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