Dillon Varone e667ee3b0c drm/amd/display: Use new num clk levels struct for max mclk index ...

[WHY?]
When calculating watermark and dlg values, the max mclk level index and
associated speed are needed to find the correlated dummy latency value.
Currently the incorrect index is given due to a clock manager refactor.

[HOW?]
Use num_memclk_level from num_entries_per_clk struct for getting the correct max
mem speed.

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2022-11-23 09:01:53 -05:00

..

calcs

drm/amd/display: Fix mutex lock in dcn10

2022-10-06 11:54:35 -04:00

dcn10

drm/amd/display: move FPU code from dcn10 to dml/dcn10 folder

2022-03-15 14:25:16 -04:00

dcn20

drm/amd/display: Enable timing sync on DCN32

2022-11-02 16:51:02 -04:00

dcn21

drm/amd/display: clean up some inconsistent indentings

2022-09-19 15:08:06 -04:00

dcn30

drm/amd/display: Mark dml30's UseMinimumDCFCLK() as noinline for stack usage

2022-09-13 14:33:01 -04:00

dcn31

drm/amd/display: always allow pstate change when no dpps are active on dcn315

2022-10-10 17:32:55 -04:00

dcn32

drm/amd/display: Use new num clk levels struct for max mclk index

2022-11-23 09:01:53 -05:00

dcn301

drm/amd/display: add debug option for dramclk_change_latency in apu

2022-09-19 15:09:05 -04:00

dcn302

drm/amd/display: move FPU associated DCN302 code to DML folder (#2266)

2022-01-18 17:42:26 -05:00

dcn303

drm/amd/display: Clean up some inconsistent indenting

2022-07-28 16:05:16 -04:00

dcn314

drm/amd/display: Update SR watermarks for DCN314

2022-11-09 17:59:10 -05:00

dcn321

drm/amd/display: Update soc bounding box for dcn32/dcn321

2022-11-23 09:01:53 -05:00

dsc

drm/display: Move DSC header and helpers into display-helper module

2022-04-25 11:19:36 +02:00

dc_features.h

drm/amd/display: Extend soc BB capabilitiy

2022-06-07 16:09:57 -04:00

display_mode_enums.h

drm/amd/display: DML changes for DCN32/321

2022-06-03 16:43:37 -04:00

display_mode_lib.c

drm/amd/display: fix dcn315 dml detile overestimation

2022-10-06 11:57:51 -04:00

display_mode_lib.h

drm/amd/display: fix dcn315 dml detile overestimation

2022-10-06 11:57:51 -04:00

display_mode_structs.h

drm/amd/display: Enforce minimum prefetch time for low memclk on DCN32

2022-11-09 18:04:13 -05:00

display_mode_vba.c

drm/amd/display: Use forced DSC bpp in DML

2022-11-02 17:16:25 -04:00

display_mode_vba.h

drm/amd/display: Fix divide by zero in DML

2022-09-13 14:32:59 -04:00

display_rq_dlg_helpers.c

drm/amdgpu/display: Remove t_srx_delay_us.

2022-01-27 15:47:34 -05:00

display_rq_dlg_helpers.h

drm/amd/display: Pass all structs in display_rq_dlg_helpers by pointer

2021-09-23 15:17:29 -04:00

dml1_display_rq_dlg_calc.c

drm/amdgpu/display: Remove t_srx_delay_us.

2022-01-27 15:47:34 -05:00

dml1_display_rq_dlg_calc.h

drm/amd/display: Fix rest of pass-by-value structs in DML

2021-09-23 15:17:30 -04:00

dml_inline_defs.h

drm/amd/display: Optimizations for DML math

2022-09-13 14:32:59 -04:00

dml_logger.h

drm/amd/display: Use MACROS instead of dm_logger

2018-03-14 15:08:45 -05:00

Makefile

drm/amd/display: Increase frame size limit for display_mode_vba_util_32.o

2022-10-18 22:13:03 -04:00