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Generally at most 1 blank line is the standard style for DT schema files. Remove the few cases with more than 1 so that the yamllint check for this can be enabled. Acked-by: Lee Jones <lee@kernel.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> # remoteproc Acked-by: Georgi Djakov <djakov@kernel.org> Acked-by: Vinod Koul <vkoul@kernel.org> Acked-by: Andi Shyti <andi.shyti@kernel.org> Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Acked-by: Jonathan Cameron <jonathan.cameron@huawei.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Uwe Kleine-König <ukleinek@kernel.org> # for allwinner,sun4i-a10-pwm.yaml Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> # mtd Acked-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com> Acked-by: Manivannan Sadhasivam <mani@kernel.org> # For PCI controller bindings Link: https://patch.msgid.link/20251023143957.2899600-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
85 lines
2.0 KiB
YAML
85 lines
2.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/gpio/fairchild,74hc595.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Generic 8-bit shift register
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description: |
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NOTE: These chips nominally don't have a chip select pin. They do however
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have a rising-edge triggered latch clock (or storage register clock) pin,
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which behaves like an active-low chip select.
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After the bits are shifted into the shift register, CS# is driven high, which
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the 74HC595 sees as a rising edge on the latch clock that results in a
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transfer of the bits from the shift register to the storage register and thus
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to the output pins.
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_ _ _ _
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shift clock ____| |_| |_..._| |_| |_________
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latch clock * trigger
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___ ________
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chip select# |___________________|
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maintainers:
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- Maxime Ripard <mripard@kernel.org>
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properties:
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compatible:
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enum:
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- fairchild,74hc595
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- nxp,74lvc594
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reg:
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maxItems: 1
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gpio-controller: true
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'#gpio-cells':
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description:
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The second cell is only used to specify the GPIO polarity.
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const: 2
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registers-number:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Number of daisy-chained shift registers
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enable-gpios:
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description: GPIO connected to the OE (Output Enable) pin.
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maxItems: 1
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patternProperties:
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"^(hog-[0-9]+|.+-hog(-[0-9]+)?)$":
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type: object
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required:
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- gpio-hog
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required:
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- compatible
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- reg
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- gpio-controller
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- '#gpio-cells'
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- registers-number
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allOf:
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- $ref: /schemas/spi/spi-peripheral-props.yaml#
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unevaluatedProperties: false
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examples:
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- |
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spi {
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#address-cells = <1>;
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#size-cells = <0>;
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gpio5@0 {
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compatible = "fairchild,74hc595";
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reg = <0>;
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gpio-controller;
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#gpio-cells = <2>;
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registers-number = <4>;
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spi-max-frequency = <100000>;
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};
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};
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