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Document the bindings for STM32MP25 PCIe Controller configured in root complex mode with one root port. Supports 4 INTx and MSI interrupts from the ARM GICv2m controller. STM32 PCIe may be in a power domain which is the case for the STM32MP25 based boards. Supports WAKE# from wake-gpios Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://patch.msgid.link/20250820075411.1178729-4-christian.bruel@foss.st.com
113 lines
3.0 KiB
YAML
113 lines
3.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/st,stm32-pcie-host.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: STMicroelectronics STM32MP25 PCIe Root Complex
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maintainers:
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- Christian Bruel <christian.bruel@foss.st.com>
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description:
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PCIe root complex controller based on the Synopsys DesignWare PCIe core.
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allOf:
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- $ref: /schemas/pci/snps,dw-pcie.yaml#
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- $ref: /schemas/pci/st,stm32-pcie-common.yaml#
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properties:
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compatible:
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const: st,stm32mp25-pcie-rc
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reg:
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items:
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- description: Data Bus Interface (DBI) registers.
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- description: PCIe configuration registers.
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reg-names:
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items:
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- const: dbi
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- const: config
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msi-parent:
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maxItems: 1
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patternProperties:
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'^pcie@[0-2],0$':
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type: object
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$ref: /schemas/pci/pci-pci-bridge.yaml#
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properties:
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reg:
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maxItems: 1
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phys:
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maxItems: 1
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reset-gpios:
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description: GPIO controlled connection to PERST# signal
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maxItems: 1
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wake-gpios:
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description: GPIO used as WAKE# input signal
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maxItems: 1
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required:
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- phys
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- ranges
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unevaluatedProperties: false
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required:
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- interrupt-map
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- interrupt-map-mask
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- ranges
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- dma-ranges
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/st,stm32mp25-rcc.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/reset/st,stm32mp25-rcc.h>
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pcie@48400000 {
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compatible = "st,stm32mp25-pcie-rc";
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device_type = "pci";
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reg = <0x48400000 0x400000>,
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<0x10000000 0x10000>;
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reg-names = "dbi", "config";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &intc 0 0 GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &intc 0 0 GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &intc 0 0 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x00000000 0x10010000 0x0 0x10000>,
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<0x02000000 0x0 0x10020000 0x10020000 0x0 0x7fe0000>,
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<0x42000000 0x0 0x18000000 0x18000000 0x0 0x8000000>;
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dma-ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x80000000>;
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clocks = <&rcc CK_BUS_PCIE>;
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resets = <&rcc PCIE_R>;
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msi-parent = <&v2m0>;
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access-controllers = <&rifsc 68>;
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power-domains = <&CLUSTER_PD>;
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pcie@0,0 {
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device_type = "pci";
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reg = <0x0 0x0 0x0 0x0 0x0>;
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phys = <&combophy PHY_TYPE_PCIE>;
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wake-gpios = <&gpioh 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
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reset-gpios = <&gpioj 8 GPIO_ACTIVE_LOW>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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};
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};
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