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On Polarfire SoC, iomux0 is responsible for routing functions to either Multiprocessor Subsystem (MSS) IOs or to the FPGA fabric, where they can either interface with custom RTL or be routed to the FPGA fabric's IOs. Document it. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
59 lines
1.4 KiB
YAML
59 lines
1.4 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip PolarFire SoC Microprocessor Subsystem (MSS) sysreg register region
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maintainers:
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- Conor Dooley <conor.dooley@microchip.com>
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description:
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An wide assortment of registers that control elements of the MSS on PolarFire
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SoC, including pinmuxing, resets and clocks among others.
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properties:
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compatible:
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items:
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- const: microchip,mpfs-mss-top-sysreg
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- const: syscon
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- const: simple-mfd
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reg:
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maxItems: 1
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'#address-cells':
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const: 1
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'#size-cells':
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const: 1
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'#reset-cells':
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description:
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The AHB/AXI peripherals on the PolarFire SoC have reset support, so
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from CLK_ENVM to CLK_CFM. The reset consumer should specify the
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desired peripheral via the clock ID in its "resets" phandle cell.
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See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list
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of PolarFire clock/reset IDs.
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const: 1
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pinctrl@200:
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type: object
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$ref: /schemas/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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syscon@20002000 {
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compatible = "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mfd";
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reg = <0x20002000 0x1000>;
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#reset-cells = <1>;
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};
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