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c3dd67681c
Add CXL region debugfs attributes to inject and clear poison based on an offset into the region. These new interfaces allow users to operate on poison at the region level without needing to resolve Device Physical Addresses (DPA) or target individual memdevs. The implementation uses a new helper, region_offset_to_dpa_result() that applies decoder interleave logic, including XOR-based address decoding when applicable. Note that XOR decodes rely on driver internal xormaps which are not exposed to userspace. So, this support is not only a simplification of poison operations that could be done using existing per memdev operations, but also it enables this functionality for XOR interleaved regions for the first time. New debugfs attributes are added in /sys/kernel/debug/cxl/regionX/: inject_poison and clear_poison. These are only exposed if all memdevs participating in the region support both inject and clear commands, ensuring consistent and reliable behavior across multi-device regions. If tracing is enabled, these operations are logged as cxl_poison events in /sys/kernel/tracing/trace. The ABI documentation warns users of the significant risks that come with using these capabilities. A CXL Maturity Map update shows this user flow is now supported. Signed-off-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Link: https://patch.msgid.link/f3fd8628ab57ea79704fb2d645902cd499c066af.1754290144.git.alison.schofield@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
203 lines
5.6 KiB
ReStructuredText
203 lines
5.6 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0
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.. include:: <isonum.txt>
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===========================================
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Compute Express Link Subsystem Maturity Map
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===========================================
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The Linux CXL subsystem tracks the dynamic `CXL specification
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<https://computeexpresslink.org/cxl-specification-landing-page>`_ that
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continues to respond to new use cases with new features, capability
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updates and fixes. At any given point some aspects of the subsystem are
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more mature than others. While the periodic pull requests summarize the
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`work being incorporated each merge window
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<https://lore.kernel.org/linux-cxl/?q=s%3APULL+s%3ACXL+tc%3Atorvalds+NOT+s%3ARe>`_,
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those do not always convey progress relative to a starting point and a
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future end goal.
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What follows is a coarse breakdown of the subsystem's major
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responsibilities along with a maturity score. The expectation is that
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the change-history of this document provides an overview summary of the
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subsystem maturation over time.
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The maturity scores are:
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- [3] Mature: Work in this area is complete and no changes on the horizon.
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Note that this score can regress from one kernel release to the next
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based on new test results or end user reports.
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- [2] Stabilizing: Major functionality operational, common cases are
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mature, but known corner cases are still a work in progress.
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- [1] Initial: Capability that has exited the Proof of Concept phase, but
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may still have significant gaps to close and fixes to apply as real
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world testing occurs.
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- [0] Known gap: Feature is on a medium to long term horizon to
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implement. If the specification has a feature that does not even have
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a '0' score in this document, there is a good chance that no one in
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the linux-cxl@vger.kernel.org community has started to look at it.
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- X: Out of scope for kernel enabling, or kernel enabling not required
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Feature and Capabilities
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========================
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Enumeration / Provisioning
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--------------------------
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All of the fundamental enumeration an object model of the subsystem is
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in place, but there are several corner cases that are pending closure.
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* [2] CXL Window Enumeration
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* [2] :ref:`Extended-linear memory-side cache <extended-linear>`
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* [0] Low Memory-hole
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* [X] Hetero-interleave
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* [2] Switch Enumeration
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* [0] CXL register enumeration link-up dependency
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* [2] HDM Decoder Configuration
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* [0] Decoder target and granularity constraints
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* [2] Performance enumeration
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* [3] Endpoint CDAT
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* [3] Switch CDAT
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* [1] CDAT to Core-mm integration
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* [1] x86
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* [0] Arm64
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* [0] All other arch.
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* [0] Shared link
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* [2] Hotplug
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(see CXL Window Enumeration)
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* [0] Handle Soft Reserved conflicts
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* [0] :ref:`RCH link status <rch-link-status>`
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* [0] Fabrics / G-FAM (chapter 7)
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* [0] Global Access Endpoint
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RAS
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---
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In many ways CXL can be seen as a standardization of what would normally
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be handled by custom EDAC drivers. The open development here is
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mainly caused by the enumeration corner cases above.
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* [3] Component events (OS)
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* [2] Component events (FFM)
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* [1] Endpoint protocol errors (OS)
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* [1] Endpoint protocol errors (FFM)
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* [0] Switch protocol errors (OS)
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* [1] Switch protocol errors (FFM)
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* [2] DPA->HPA Address translation
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* [1] XOR Interleave translation
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(see CXL Window Enumeration)
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* [1] Memory Failure coordination
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* [0] Scrub control
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* [2] ACPI error injection EINJ
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* [0] EINJ v2
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* [X] Compliance DOE
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* [2] Native error injection
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* [3] RCH error handling
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* [1] VH error handling
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* [0] PPR
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* [0] Sparing
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* [0] Device built in test
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Mailbox commands
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----------------
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* [3] Firmware update
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* [3] Health / Alerts
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* [1] :ref:`Background commands <background-commands>`
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* [3] Sanitization
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* [3] Security commands
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* [3] RAW Command Debug Passthrough
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* [0] CEL-only-validation Passthrough
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* [0] Switch CCI
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* [3] Timestamp
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* [1] PMEM labels
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* [3] PMEM GPF / Dirty Shutdown
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* [0] Scan Media
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PMU
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---
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* [1] Type 3 PMU
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* [0] Switch USP/ DSP, Root Port
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Security
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--------
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* [X] CXL Trusted Execution Environment Security Protocol (TSP)
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* [X] CXL IDE (subsumed by TSP)
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Memory-pooling
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--------------
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* [1] Hotplug of LDs (via PCI hotplug)
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* [0] Dynamic Capacity Device (DCD) Support
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Multi-host sharing
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------------------
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* [0] Hardware coherent shared memory
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* [0] Software managed coherency shared memory
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Multi-host memory
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-----------------
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* [0] Dynamic Capacity Device Support
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* [0] Sharing
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Accelerator
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-----------
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* [0] Accelerator memory enumeration HDM-D (CXL 1.1/2.0 Type-2)
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* [0] Accelerator memory enumeration HDM-DB (CXL 3.0 Type-2)
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* [0] CXL.cache 68b (CXL 2.0)
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* [0] CXL.cache 256b Cache IDs (CXL 3.0)
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User Flow Support
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-----------------
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* [2] Inject & clear poison by region offset
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Details
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=======
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.. _extended-linear:
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* **Extended-linear memory-side cache**: An HMAT proposal to enumerate the presence of a
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memory-side cache where the cache capacity extends the SRAT address
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range capacity. `See the ECN
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<https://lore.kernel.org/linux-cxl/6650e4f835a0e_195e294a8@dwillia2-mobl3.amr.corp.intel.com.notmuch/>`_
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for more details:
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.. _rch-link-status:
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* **RCH Link Status**: RCH (Restricted CXL Host) topologies, end up
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hiding some standard registers like PCIe Link Status / Capabilities in
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the CXL RCRB (Root Complex Register Block).
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.. _background-commands:
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* **Background commands**: The CXL background command mechanism is
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awkward as the single slot is monopolized potentially indefinitely by
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various commands. A `cancel on conflict
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<http://lore.kernel.org/r/66035c2e8ba17_770232948b@dwillia2-xfh.jf.intel.com.notmuch>`_
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facility is needed to make sure the kernel can ensure forward progress
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of priority commands.
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