Relja Vojvodic 81557c96c8 drm/amd/display: Correct slice width calculation for YCbCr420 ...

[Why]
-OVT compliance testing for 5120x2880p300Hz YCbCr420 was failing due to
incorrect slice width being calculated

[How]
-Ensure slice width is divisible by 2 for 420 to comply with spec

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Relja Vojvodic <rvojvodi@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2025-10-13 14:14:31 -04:00

..

dcn32_hwseq.c

drm/amd/display: Correct slice width calculation for YCbCr420

2025-10-13 14:14:31 -04:00

dcn32_hwseq.h

drm/amd/display: Unify blank_phantom and blank_pixel_data

2024-10-07 14:10:21 -04:00

dcn32_init.c

drm/amd/display: Adding interface to log hw state when underflow happens

2025-08-04 14:40:32 -04:00

dcn32_init.h

drm/amd/display: Refactor INIT into component folder

2024-01-03 10:47:29 -05:00