Ovidiu Bunea 1bde5584e2 drm/amd/display: Correct sequences and delays for DCN35 PG & RCG ...

[why]
The current PG & RCG programming in driver has some gaps and incorrect
sequences.

[how]
Added delays after ungating clocks to allow ramp up, increased polling
to allow more time for power up, and removed the incorrect sequences.

Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2025-09-05 17:38:41 -04:00

..

dcn351_hwseq.c

drm/amd/display: Modify power sequence

2024-04-12 00:36:40 -04:00

dcn351_hwseq.h

drm/amd/display: Modify power sequence

2024-04-12 00:36:40 -04:00

dcn351_init.c

drm/amd/display: Correct sequences and delays for DCN35 PG & RCG

2025-09-05 17:38:41 -04:00

dcn351_init.h

drm/amd/display: Refactor INIT into component folder

2024-01-03 10:47:29 -05:00

Makefile

drm/amd/display: Modify power sequence

2024-04-12 00:36:40 -04:00