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Hook up the LT Phy enable and disable sequences using encoder-> enable/disable_clock and reusing the TBT enable disable sequence from cx0 PHY since it remains the same. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-18-suraj.kandpal@intel.com
71 lines
2.8 KiB
C
71 lines
2.8 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef __INTEL_CX0_PHY_H__
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#define __INTEL_CX0_PHY_H__
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#include <linux/types.h>
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#define MB_WRITE_COMMITTED true
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#define MB_WRITE_UNCOMMITTED false
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enum icl_port_dpll_id;
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struct intel_atomic_state;
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struct intel_c10pll_state;
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struct intel_c20pll_state;
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struct intel_crtc;
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struct intel_crtc_state;
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struct intel_cx0pll_state;
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struct intel_display;
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struct intel_encoder;
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struct intel_hdmi;
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void intel_clear_response_ready_flag(struct intel_encoder *encoder,
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int lane);
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bool intel_encoder_is_c10phy(struct intel_encoder *encoder);
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void intel_mtl_pll_enable(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state);
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void intel_mtl_pll_disable(struct intel_encoder *encoder);
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enum icl_port_dpll_id
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intel_mtl_port_pll_type(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state);
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int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder);
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void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
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struct intel_cx0pll_state *pll_state);
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int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
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const struct intel_cx0pll_state *pll_state);
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void intel_cx0pll_dump_hw_state(struct intel_display *display,
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const struct intel_cx0pll_state *hw_state);
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void intel_cx0pll_state_verify(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a,
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const struct intel_cx0pll_state *b);
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void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state);
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void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
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u8 lane_mask, u8 state);
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int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
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void intel_cx0_setup_powerdown(struct intel_encoder *encoder);
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bool intel_cx0_is_hdmi_frl(u32 clock);
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u8 intel_cx0_read(struct intel_encoder *encoder, u8 lane_mask, u16 addr);
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void intel_cx0_rmw(struct intel_encoder *encoder,
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u8 lane_mask, u16 addr, u8 clear, u8 set, bool committed);
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void intel_cx0_write(struct intel_encoder *encoder,
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u8 lane_mask, u16 addr, u8 data, bool committed);
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int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
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int command, int lane, u32 *val);
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void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane);
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int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
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void intel_cx0_pll_power_save_wa(struct intel_display *display);
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void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state);
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void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state);
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void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder);
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#endif /* __INTEL_CX0_PHY_H__ */
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