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8d0f798862
Add support for the newer HDMI-TX (Encoder) v2 and DDC v2 IPs found in MediaTek's MT8195, MT8188 SoC and their variants, and including support for display modes up to 4k60 and for HDMI Audio, as per the HDMI 2.0 spec. HDCP and CEC functionalities are also supported by this hardware, but are not included in this commit and that also poses a slight difference between the V2 and V1 controllers in how they handle Hotplug Detection (HPD). While the v1 controller was using the CEC controller to check HDMI cable connection and disconnection, in this driver the v2 one does not. This is due to the fact that on parts with v2 designs, like the MT8195 SoC, there is one CEC controller shared between the HDMI Transmitter (HDMI-TX) and Receiver (HDMI-RX): before eventually adding support to use the CEC HW to wake up the HDMI controllers it is necessary to have support for one TX, one RX *and* for both at the same time. Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20251023-mediatek-drm-hdmi-v2-v11-9-7873ec4a1edf@collabora.com/ Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> ddc_v2 ddc_v2
199 lines
5.2 KiB
C
199 lines
5.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021 MediaTek Inc.
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* Copyright (c) 2024 Collabora Ltd.
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*/
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#ifndef _MTK_HDMI_COMMON_H
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#define _MTK_HDMI_COMMON_H
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_bridge.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_edid.h>
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#include <drm/drm_print.h>
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/hdmi.h>
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#include <linux/i2c.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mutex.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <sound/hdmi-codec.h>
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enum hdmi_aud_input_type {
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HDMI_AUD_INPUT_I2S = 0,
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HDMI_AUD_INPUT_SPDIF,
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};
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enum hdmi_aud_i2s_fmt {
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HDMI_I2S_MODE_RJT_24BIT = 0,
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HDMI_I2S_MODE_RJT_16BIT,
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HDMI_I2S_MODE_LJT_24BIT,
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HDMI_I2S_MODE_LJT_16BIT,
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HDMI_I2S_MODE_I2S_24BIT,
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HDMI_I2S_MODE_I2S_16BIT
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};
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enum hdmi_aud_mclk {
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HDMI_AUD_MCLK_128FS,
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HDMI_AUD_MCLK_192FS,
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HDMI_AUD_MCLK_256FS,
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HDMI_AUD_MCLK_384FS,
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HDMI_AUD_MCLK_512FS,
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HDMI_AUD_MCLK_768FS,
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HDMI_AUD_MCLK_1152FS,
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};
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enum hdmi_aud_channel_type {
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HDMI_AUD_CHAN_TYPE_1_0 = 0,
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HDMI_AUD_CHAN_TYPE_1_1,
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HDMI_AUD_CHAN_TYPE_2_0,
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HDMI_AUD_CHAN_TYPE_2_1,
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HDMI_AUD_CHAN_TYPE_3_0,
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HDMI_AUD_CHAN_TYPE_3_1,
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HDMI_AUD_CHAN_TYPE_4_0,
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HDMI_AUD_CHAN_TYPE_4_1,
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HDMI_AUD_CHAN_TYPE_5_0,
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HDMI_AUD_CHAN_TYPE_5_1,
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HDMI_AUD_CHAN_TYPE_6_0,
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HDMI_AUD_CHAN_TYPE_6_1,
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HDMI_AUD_CHAN_TYPE_7_0,
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HDMI_AUD_CHAN_TYPE_7_1,
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HDMI_AUD_CHAN_TYPE_3_0_LRS,
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HDMI_AUD_CHAN_TYPE_3_1_LRS,
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HDMI_AUD_CHAN_TYPE_4_0_CLRS,
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HDMI_AUD_CHAN_TYPE_4_1_CLRS,
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HDMI_AUD_CHAN_TYPE_6_1_CS,
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HDMI_AUD_CHAN_TYPE_6_1_CH,
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HDMI_AUD_CHAN_TYPE_6_1_OH,
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HDMI_AUD_CHAN_TYPE_6_1_CHR,
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HDMI_AUD_CHAN_TYPE_7_1_LH_RH,
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HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR,
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HDMI_AUD_CHAN_TYPE_7_1_LC_RC,
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HDMI_AUD_CHAN_TYPE_7_1_LW_RW,
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HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD,
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HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS,
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HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS,
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HDMI_AUD_CHAN_TYPE_7_1_CS_CH,
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HDMI_AUD_CHAN_TYPE_7_1_CS_OH,
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HDMI_AUD_CHAN_TYPE_7_1_CS_CHR,
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HDMI_AUD_CHAN_TYPE_7_1_CH_OH,
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HDMI_AUD_CHAN_TYPE_7_1_CH_CHR,
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HDMI_AUD_CHAN_TYPE_7_1_OH_CHR,
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HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR,
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HDMI_AUD_CHAN_TYPE_6_0_CS,
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HDMI_AUD_CHAN_TYPE_6_0_CH,
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HDMI_AUD_CHAN_TYPE_6_0_OH,
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HDMI_AUD_CHAN_TYPE_6_0_CHR,
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HDMI_AUD_CHAN_TYPE_7_0_LH_RH,
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HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR,
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HDMI_AUD_CHAN_TYPE_7_0_LC_RC,
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HDMI_AUD_CHAN_TYPE_7_0_LW_RW,
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HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD,
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HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS,
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HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS,
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HDMI_AUD_CHAN_TYPE_7_0_CS_CH,
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HDMI_AUD_CHAN_TYPE_7_0_CS_OH,
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HDMI_AUD_CHAN_TYPE_7_0_CS_CHR,
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HDMI_AUD_CHAN_TYPE_7_0_CH_OH,
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HDMI_AUD_CHAN_TYPE_7_0_CH_CHR,
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HDMI_AUD_CHAN_TYPE_7_0_OH_CHR,
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HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR,
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HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS,
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HDMI_AUD_CHAN_TYPE_UNKNOWN = 0xFF
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};
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enum hdmi_aud_channel_swap_type {
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HDMI_AUD_SWAP_LR,
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HDMI_AUD_SWAP_LFE_CC,
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HDMI_AUD_SWAP_LSRS,
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HDMI_AUD_SWAP_RLS_RRS,
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HDMI_AUD_SWAP_LR_STATUS,
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};
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struct hdmi_audio_param {
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enum hdmi_audio_coding_type aud_codec;
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enum hdmi_audio_sample_size aud_sample_size;
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enum hdmi_aud_input_type aud_input_type;
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enum hdmi_aud_i2s_fmt aud_i2s_fmt;
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enum hdmi_aud_mclk aud_mclk;
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enum hdmi_aud_channel_type aud_input_chan_type;
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struct hdmi_codec_params codec_params;
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};
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enum hdmi_hpd_state {
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HDMI_PLUG_OUT = 0,
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HDMI_PLUG_IN_AND_SINK_POWER_ON,
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HDMI_PLUG_IN_ONLY,
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};
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struct mtk_hdmi_ver_conf {
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const struct drm_bridge_funcs *bridge_funcs;
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const struct hdmi_codec_ops *codec_ops;
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const char * const *mtk_hdmi_clock_names;
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int num_clocks;
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bool interlace_allowed;
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};
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struct mtk_hdmi_conf {
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const struct mtk_hdmi_ver_conf *ver_conf;
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bool tz_disabled;
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bool cea_modes_only;
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unsigned long max_mode_clock;
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u32 reg_hdmi_tx_cfg;
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};
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struct mtk_hdmi {
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struct drm_bridge bridge;
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struct drm_bridge *next_bridge;
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struct drm_connector *curr_conn;/* current connector (only valid when 'enabled') */
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struct device *dev;
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const struct mtk_hdmi_conf *conf;
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struct phy *phy;
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struct device *cec_dev;
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struct i2c_adapter *ddc_adpt;
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struct clk **clk;
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struct drm_display_mode mode;
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bool dvi_mode;
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struct regmap *sys_regmap;
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unsigned int sys_offset;
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struct regmap *regs;
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struct platform_device *audio_pdev;
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struct hdmi_audio_param aud_param;
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bool audio_enable;
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bool powered;
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bool enabled;
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unsigned int irq;
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enum hdmi_hpd_state hpd;
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hdmi_codec_plugged_cb plugged_cb;
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struct device *codec_dev;
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struct mutex update_plugged_status_lock;
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};
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static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
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{
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return container_of(b, struct mtk_hdmi, bridge);
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}
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int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len);
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void mtk_hdmi_audio_set_plugged_cb(struct mtk_hdmi *hdmi, hdmi_codec_plugged_cb fn,
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struct device *codec_dev);
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int mtk_hdmi_audio_params(struct mtk_hdmi *hdmi, struct hdmi_codec_daifmt *daifmt,
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struct hdmi_codec_params *params);
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void mtk_hdmi_get_ncts(unsigned int sample_rate, unsigned int clock,
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unsigned int *n, unsigned int *cts);
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bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
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const struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode);
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void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge,
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const struct drm_display_mode *mode,
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const struct drm_display_mode *adjusted_mode);
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struct mtk_hdmi *mtk_hdmi_common_probe(struct platform_device *pdev);
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#endif /* _MTK_HDMI_COMMON_H */
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