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31d3354f42
Ensure that the DMA address of the framebuffer flush page is not larger than its hardware register. On GPUs older than Hopper, the register for the address can hold up to a 40-bit address (right-shifted by 8 so that it fits in the 32-bit register), and on Hopper and later it can be 52 bits (64-bit register where bits 52-63 must be zero). Recently it was discovered that under certain conditions, the flush page could be allocated outside this range. Although this bug was fixed, we can ensure that any future changes to this code don't accidentally generate an invalid page address. Signed-off-by: Timur Tabi <ttabi@nvidia.com> Reviewed-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Lyude Paul <lyude@redhat.com> Link: https://patch.msgid.link/20251113230323.1271726-2-ttabi@nvidia.com
140 lines
3.8 KiB
C
140 lines
3.8 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "gf100.h"
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#include "ram.h"
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#include <core/memory.h>
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#include <core/option.h>
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#include <subdev/therm.h>
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void
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gf100_fb_intr(struct nvkm_fb *base)
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{
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struct gf100_fb *fb = gf100_fb(base);
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struct nvkm_subdev *subdev = &fb->base.subdev;
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struct nvkm_device *device = subdev->device;
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u32 intr = nvkm_rd32(device, 0x000100);
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if (intr & 0x08000000)
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nvkm_debug(subdev, "PFFB intr\n");
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if (intr & 0x00002000)
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nvkm_debug(subdev, "PBFB intr\n");
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}
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int
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gf100_fb_oneinit(struct nvkm_fb *base)
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{
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struct gf100_fb *fb = gf100_fb(base);
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struct nvkm_device *device = fb->base.subdev.device;
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int ret, size = 1 << (fb->base.page ? fb->base.page : 17);
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size = nvkm_longopt(device->cfgopt, "MmuDebugBufferSize", size);
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size = max(size, 0x1000);
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ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, size, 0x1000,
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true, &fb->base.mmu_rd);
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if (ret)
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return ret;
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ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, size, 0x1000,
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true, &fb->base.mmu_wr);
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if (ret)
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return ret;
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return 0;
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}
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int
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gf100_fb_init_page(struct nvkm_fb *fb)
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{
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struct nvkm_device *device = fb->subdev.device;
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switch (fb->page) {
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case 16: nvkm_mask(device, 0x100c80, 0x00000001, 0x00000001); break;
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case 17: nvkm_mask(device, 0x100c80, 0x00000001, 0x00000000); break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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void
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gf100_fb_sysmem_flush_page_init(struct nvkm_fb *fb)
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{
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// Ensure that the address can actually fit in the register
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WARN_ON(fb->sysmem.flush_page_addr > DMA_BIT_MASK(40));
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nvkm_wr32(fb->subdev.device, 0x100c10, fb->sysmem.flush_page_addr >> 8);
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}
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void
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gf100_fb_init(struct nvkm_fb *base)
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{
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struct gf100_fb *fb = gf100_fb(base);
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struct nvkm_device *device = fb->base.subdev.device;
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if (base->func->clkgate_pack) {
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nvkm_therm_clkgate_init(device->therm,
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base->func->clkgate_pack);
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}
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}
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void *
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gf100_fb_dtor(struct nvkm_fb *base)
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{
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struct gf100_fb *fb = gf100_fb(base);
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return fb;
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}
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int
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gf100_fb_new_(const struct nvkm_fb_func *func, struct nvkm_device *device,
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enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
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{
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struct gf100_fb *fb;
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if (!(fb = kzalloc(sizeof(*fb), GFP_KERNEL)))
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return -ENOMEM;
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nvkm_fb_ctor(func, device, type, inst, &fb->base);
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*pfb = &fb->base;
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return 0;
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}
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static const struct nvkm_fb_func
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gf100_fb = {
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.dtor = gf100_fb_dtor,
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.oneinit = gf100_fb_oneinit,
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.init = gf100_fb_init,
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.init_page = gf100_fb_init_page,
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.intr = gf100_fb_intr,
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.sysmem.flush_page_init = gf100_fb_sysmem_flush_page_init,
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.ram_new = gf100_ram_new,
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.default_bigpage = 17,
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};
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int
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gf100_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
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{
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return gf100_fb_new_(&gf100_fb, device, type, inst, pfb);
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}
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