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1e12dbae9d
Make this the default on xe2+ when doing a copy. This has a few
advantages over the exiting copy instruction:
1) It has a special PAGE_COPY mode that claims to be optimised for
page-in/page-out, which is the vast majority of current users.
2) It also has a simple BYTE_COPY mode that supports byte granularity
copying without any restrictions.
With 2) we can now easily skip the bounce buffer flow when copying
buffers with strange sizing/alignment, like for memory_access. But that
is left for the next patch.
v2 (Matt Brost):
- Use device info to check whether device should use the MEM_COPY
path. This should fit better with making this a configfs tunable.
- And with that also keep old path still functional on xe2 for possible
experimentation.
- Add a define for PAGE_COPY page-size.
v3 (Matt Brost):
- Fallback to an actual linear copy for pitch=1.
- Also update NVL.
BSpec: 57561
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Link: https://lore.kernel.org/r/20251022163836.191405-7-matthew.auld@intel.com
78 lines
3.1 KiB
C
78 lines
3.1 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef _XE_GPU_COMMANDS_H_
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#define _XE_GPU_COMMANDS_H_
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#include "regs/xe_reg_defs.h"
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#define XY_CTRL_SURF_COPY_BLT ((2 << 29) | (0x48 << 22) | 3)
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#define SRC_ACCESS_TYPE_SHIFT 21
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#define DST_ACCESS_TYPE_SHIFT 20
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#define CCS_SIZE_MASK GENMASK(17, 8)
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#define XE2_CCS_SIZE_MASK GENMASK(18, 9)
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#define XY_CTRL_SURF_MOCS_MASK GENMASK(31, 26)
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#define XE2_XY_CTRL_SURF_MOCS_INDEX_MASK GENMASK(31, 28)
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#define NUM_CCS_BYTES_PER_BLOCK 256
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#define NUM_BYTES_PER_CCS_BYTE(_xe) (GRAPHICS_VER(_xe) >= 20 ? 512 : 256)
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#define XY_FAST_COLOR_BLT_CMD (2 << 29 | 0x44 << 22)
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#define XY_FAST_COLOR_BLT_DEPTH_32 (2 << 19)
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#define XY_FAST_COLOR_BLT_DW 16
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#define XY_FAST_COLOR_BLT_MOCS_MASK GENMASK(27, 22)
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#define XE2_XY_FAST_COLOR_BLT_MOCS_INDEX_MASK GENMASK(27, 24)
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#define XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT 31
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#define XY_FAST_COPY_BLT_CMD (2 << 29 | 0x42 << 22)
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#define XY_FAST_COPY_BLT_DEPTH_32 (3<<24)
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#define XY_FAST_COPY_BLT_D1_SRC_TILE4 REG_BIT(31)
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#define XY_FAST_COPY_BLT_D1_DST_TILE4 REG_BIT(30)
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#define XE2_XY_FAST_COPY_BLT_MOCS_INDEX_MASK GENMASK(23, 20)
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#define MEM_COPY_CMD (2 << 29 | 0x5a << 22 | 0x8)
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#define MEM_COPY_PAGE_COPY_MODE REG_BIT(19)
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#define MEM_COPY_MATRIX_COPY REG_BIT(17)
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#define MEM_COPY_SRC_MOCS_INDEX_MASK GENMASK(31, 28)
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#define MEM_COPY_DST_MOCS_INDEX_MASK GENMASK(6, 3)
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#define PVC_MEM_SET_CMD (2 << 29 | 0x5b << 22)
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#define PVC_MEM_SET_CMD_LEN_DW 7
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#define PVC_MEM_SET_MATRIX REG_BIT(17)
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#define PVC_MEM_SET_DATA_FIELD GENMASK(31, 24)
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/* Bspec lists field as [6:0], but index alone is from [6:1] */
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#define PVC_MEM_SET_MOCS_INDEX_MASK GENMASK(6, 1)
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#define XE2_MEM_SET_MOCS_INDEX_MASK GENMASK(6, 3)
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#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
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#define PIPE_CONTROL0_L3_READ_ONLY_CACHE_INVALIDATE BIT(10) /* gen12 */
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#define PIPE_CONTROL0_HDC_PIPELINE_FLUSH BIT(9) /* gen12 */
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#define PIPE_CONTROL_COMMAND_CACHE_INVALIDATE (1<<29)
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#define PIPE_CONTROL_TILE_CACHE_FLUSH (1<<28)
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#define PIPE_CONTROL_AMFS_FLUSH (1<<25)
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#define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24)
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#define PIPE_CONTROL_LRI_POST_SYNC BIT(23)
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#define PIPE_CONTROL_STORE_DATA_INDEX (1<<21)
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#define PIPE_CONTROL_CS_STALL (1<<20)
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#define PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET (1<<19)
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#define PIPE_CONTROL_TLB_INVALIDATE BIT(18)
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#define PIPE_CONTROL_PSD_SYNC (1<<17)
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#define PIPE_CONTROL_QW_WRITE (1<<14)
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#define PIPE_CONTROL_DEPTH_STALL (1<<13)
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#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12)
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#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11)
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#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10)
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#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
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#define PIPE_CONTROL_FLUSH_ENABLE (1<<7)
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#define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5)
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#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
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#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)
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#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)
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#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
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#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
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#endif
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