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Starting from Xe3p, there are two different copies of some of the GAM registers: the traditional MCR variant at their old locations, and a new unicast copy known as "main_gamctrl." The Xe driver doesn't use these registers directly, but we need to instruct the GuC on which set it should use. Since the new, unicast registers are preferred (since they avoid the need for unnecessary MCR synchronization), set a new GuC feature flag, GUC_CTL_MAIN_GAMCTRL_QUEUES to convey this decision. A new helper function, xe_guc_using_main_gamctrl_queues(), is added for use in the 3 independent places that need to handle configuration of the new reporting queues. The mmio write to enable the main gamctl is only done during the general GuC upload. The gamctrl registers are not accessed by the GuC during hwconfig load. Last, the ADS blob for communicating the queue addresses contains both a DPA and GGTT offset. The GuC documentation states that DPA is now MBZ when using the MAIN_GAMCTRL queues. Bspec: 76445, 73540 Signed-off-by: Brian Welty <brian.welty@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://lore.kernel.org/r/20251019-xe3p-gamctrl-v1-1-ad66d3c1908f@intel.com Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
98 lines
3.0 KiB
C
98 lines
3.0 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#ifndef _XE_GUC_H_
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#define _XE_GUC_H_
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#include "xe_gt.h"
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#include "xe_guc_types.h"
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#include "xe_hw_engine_types.h"
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#include "xe_macros.h"
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/*
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* GuC version number components are defined to be only 8-bit size,
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* so converting to a 32bit 8.8.8 integer allows simple (and safe)
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* numerical comparisons.
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*/
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#define MAKE_GUC_VER(maj, min, pat) (((maj) << 16) | ((min) << 8) | (pat))
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#define MAKE_GUC_VER_STRUCT(ver) MAKE_GUC_VER((ver).major, (ver).minor, (ver).patch)
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#define GUC_SUBMIT_VER(guc) \
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MAKE_GUC_VER_STRUCT((guc)->fw.versions.found[XE_UC_FW_VER_COMPATIBILITY])
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#define GUC_FIRMWARE_VER(guc) \
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MAKE_GUC_VER_STRUCT((guc)->fw.versions.found[XE_UC_FW_VER_RELEASE])
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struct drm_printer;
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void xe_guc_comm_init_early(struct xe_guc *guc);
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int xe_guc_init_noalloc(struct xe_guc *guc);
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int xe_guc_init(struct xe_guc *guc);
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int xe_guc_init_post_hwconfig(struct xe_guc *guc);
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int xe_guc_post_load_init(struct xe_guc *guc);
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int xe_guc_reset(struct xe_guc *guc);
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int xe_guc_upload(struct xe_guc *guc);
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int xe_guc_min_load_for_hwconfig(struct xe_guc *guc);
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int xe_guc_enable_communication(struct xe_guc *guc);
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int xe_guc_opt_in_features_enable(struct xe_guc *guc);
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int xe_guc_suspend(struct xe_guc *guc);
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void xe_guc_notify(struct xe_guc *guc);
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int xe_guc_auth_huc(struct xe_guc *guc, u32 rsa_addr);
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int xe_guc_mmio_send(struct xe_guc *guc, const u32 *request, u32 len);
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int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request, u32 len,
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u32 *response_buf);
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int xe_guc_self_cfg32(struct xe_guc *guc, u16 key, u32 val);
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int xe_guc_self_cfg64(struct xe_guc *guc, u16 key, u64 val);
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void xe_guc_irq_handler(struct xe_guc *guc, const u16 iir);
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void xe_guc_sanitize(struct xe_guc *guc);
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void xe_guc_print_info(struct xe_guc *guc, struct drm_printer *p);
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int xe_guc_reset_prepare(struct xe_guc *guc);
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void xe_guc_reset_wait(struct xe_guc *guc);
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void xe_guc_stop_prepare(struct xe_guc *guc);
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void xe_guc_stop(struct xe_guc *guc);
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int xe_guc_start(struct xe_guc *guc);
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void xe_guc_declare_wedged(struct xe_guc *guc);
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bool xe_guc_using_main_gamctrl_queues(struct xe_guc *guc);
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#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
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int xe_guc_g2g_test_notification(struct xe_guc *guc, u32 *payload, u32 len);
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#endif
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static inline u16 xe_engine_class_to_guc_class(enum xe_engine_class class)
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{
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switch (class) {
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case XE_ENGINE_CLASS_RENDER:
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return GUC_RENDER_CLASS;
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case XE_ENGINE_CLASS_VIDEO_DECODE:
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return GUC_VIDEO_CLASS;
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case XE_ENGINE_CLASS_VIDEO_ENHANCE:
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return GUC_VIDEOENHANCE_CLASS;
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case XE_ENGINE_CLASS_COPY:
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return GUC_BLITTER_CLASS;
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case XE_ENGINE_CLASS_COMPUTE:
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return GUC_COMPUTE_CLASS;
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case XE_ENGINE_CLASS_OTHER:
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return GUC_GSC_OTHER_CLASS;
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default:
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XE_WARN_ON(class);
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return -1;
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}
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}
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static inline struct xe_gt *guc_to_gt(struct xe_guc *guc)
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{
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return container_of(guc, struct xe_gt, uc.guc);
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}
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static inline struct xe_device *guc_to_xe(struct xe_guc *guc)
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{
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return gt_to_xe(guc_to_gt(guc));
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}
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static inline struct drm_device *guc_to_drm(struct xe_guc *guc)
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{
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return &guc_to_xe(guc)->drm;
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}
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#endif
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