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789a5913b2
Replace the io_pgtable versions with pt_iommu versions. The v2 page table
uses the x86 implementation that will be eventually shared with VT-d.
This supports the same special features as the original code:
- increase_top for the v1 format to allow scaling from 3 to 6 levels
- non-present flushing
- Dirty tracking for v1 only
- __sme_set() to adjust the PTEs for CC
- Optimization for flushing with virtualization to minimize the range
- amd_iommu_pgsize_bitmap override of the native page sizes
- page tables allocate from the device's NUMA node
Rework the domain ops so that v1/v2 get their own ops. Make dedicated
allocation functions for v1 and v2. Hook up invalidation for a top change
to struct pt_iommu_flush_ops. Delete some of the iopgtable related code
that becomes unused in this patch. The next patch will delete the rest of
it.
This fixes a race bug in AMD's increase_address_space() implementation. It
stores the top level and top pointer in different memory, which prevents
other threads from reading a coherent version:
increase_address_space() alloc_pte()
level = pgtable->mode - 1;
pgtable->root = pte;
pgtable->mode += 1;
pte = &pgtable->root[PM_LEVEL_INDEX(level, address)];
The iommupt version is careful to put mode and root under a single
READ_ONCE and then is careful to only READ_ONCE a single time per
walk.
Signed-off-by: Alejandro Jimenez <alejandro.j.jimenez@oracle.com>
Reviewed-by: Vasant Hegde <vasant.hegde@amd.com>
Tested-by: Alejandro Jimenez <alejandro.j.jimenez@oracle.com>
Tested-by: Pasha Tatashin <pasha.tatashin@soleen.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
44 lines
1.3 KiB
Plaintext
44 lines
1.3 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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# AMD IOMMU support
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config AMD_IOMMU
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bool "AMD IOMMU support"
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select SWIOTLB
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select PCI_MSI
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select PCI_ATS
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select PCI_PRI
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select PCI_PASID
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select IRQ_MSI_LIB
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select MMU_NOTIFIER
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select IOMMU_API
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select IOMMU_IOVA
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select IOMMU_SVA
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select IOMMU_IOPF
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select IOMMUFD_DRIVER if IOMMUFD
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select GENERIC_PT
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select IOMMU_PT
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select IOMMU_PT_AMDV1
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select IOMMU_PT_X86_64
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depends on X86_64 && PCI && ACPI && HAVE_CMPXCHG_DOUBLE
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help
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With this option you can enable support for AMD IOMMU hardware in
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your system. An IOMMU is a hardware component which provides
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remapping of DMA memory accesses from devices. With an AMD IOMMU you
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can isolate the DMA memory of different devices and protect the
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system from misbehaving device drivers or hardware.
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You can find out if your system has an AMD IOMMU if you look into
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your BIOS for an option to enable it or if you have an IVRS ACPI
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table.
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config AMD_IOMMU_DEBUGFS
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bool "Enable AMD IOMMU internals in DebugFS"
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depends on AMD_IOMMU && IOMMU_DEBUGFS
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help
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!!!WARNING!!! !!!WARNING!!! !!!WARNING!!! !!!WARNING!!!
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DO NOT ENABLE THIS OPTION UNLESS YOU REALLY, -REALLY- KNOW WHAT YOU ARE DOING!!!
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Exposes AMD IOMMU device internals in DebugFS.
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This option is -NOT- intended for production environments, and should
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not generally be enabled.
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