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22335939ec
Add driver for the MaxLinear GSW1xx family of Ethernet switch ICs which are based on the same IP as the Lantiq/Intel GSWIP found in the Lantiq VR9 and Intel GRX MIPS router SoCs. The main difference is that instead of using memory-mapped I/O to communicate with the host CPU these ICs are connected via MDIO (or SPI, which isn't supported by this driver). Implement the regmap API to access the switch registers over MDIO to allow reusing lantiq_gswip_common for all core functionality. The GSW1xx also comes with a SerDes port capable of 1000Base-X, SGMII and 2500Base-X, which can either be used to connect an external PHY or SFP cage, or as the CPU port. Support for the SerDes interface is implemented in this driver using the phylink_pcs interface. Signed-off-by: Daniel Golle <daniel@makrotopia.org> Tested-by: Alexander Sverdlin <alexander.sverdlin@siemens.com> Link: https://patch.msgid.link/b567ec1b4beb08fd37abf18b280c56d5d8253c26.1762170107.git.daniel@makrotopia.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
25 lines
812 B
Plaintext
25 lines
812 B
Plaintext
config NET_DSA_LANTIQ_COMMON
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tristate
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select REGMAP
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config NET_DSA_LANTIQ_GSWIP
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tristate "Lantiq / Intel GSWIP"
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depends on HAS_IOMEM
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select NET_DSA_TAG_GSWIP
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select NET_DSA_LANTIQ_COMMON
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help
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This enables support for the Lantiq / Intel GSWIP 2.1 found in
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the xrx200 / VR9 SoC.
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config NET_DSA_MXL_GSW1XX
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tristate "MaxLinear GSW1xx Ethernet switch support"
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select NET_DSA_TAG_MXL_GSW1XX
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select NET_DSA_LANTIQ_COMMON
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help
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This enables support for the MaxLinear GSW1xx family of 1GE switches
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GSW120 4 port, 2 PHYs, RGMII & SGMII/2500Base-X
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GSW125 4 port, 2 PHYs, RGMII & SGMII/2500Base-X, industrial temperature
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GSW140 6 port, 4 PHYs, RGMII & SGMII/2500Base-X
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GSW141 6 port, 4 PHYs, RGMII & SGMII
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GSW145 6 port, 4 PHYs, RGMII & SGMII/2500Base-X, industrial temperature
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