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E830 supports Earliest TxTime First (ETF) hardware offload, which is configured via the ETF Qdisc on a per-queue basis (see tc-etf(8)). ETF introduces a new Tx flow mechanism that utilizes a timestamp ring (tstamp_ring) alongside the standard Tx ring. This timestamp ring is used to indicate when hardware will transmit a packet. Tx Time is supported on the first 2048 Tx queues of the device, and the NVM image limits the maximum number of Tx queues to 2048 for the device. The allocation and initialization of the timestamp ring occur when the feature is enabled on a specific Tx queue via tc-etf. The requested Tx Time queue index cannot be greater than the number of Tx queues (vsi->num_txq). To support ETF, the following flags and bitmap are introduced: - ICE_F_TXTIME: Device feature flag set for E830 NICs, indicating ETF support. - txtime_txqs: PF-level bitmap set when ETF is enabled and cleared when disabled for a specific Tx queue. It is used by ice_is_txtime_ena() to check if ETF is allocated and configured on any Tx queue, which is checked during Tx ring allocation. - ICE_TX_FLAGS_TXTIME: Per Tx ring flag set when ETF is allocated and configured for a specific Tx queue. It determines ETF status during packet transmission and is checked by ice_is_txtime_ena() to verify if ETF is enabled on any Tx queue. Due to a hardware issue that can result in a malicious driver detection event, additional timestamp descriptors are required when wrapping around the timestamp ring. Up to 64 additional timestamp descriptors are reserved, reducing the available Tx descriptors. To accommodate this, ICE_MAX_NUM_DESC_BY_MAC is introduced, defining: - E830: Maximum Tx descriptor count of 8096 (8K - 32 - 64 for timestamp fetch descriptors). - E810 and E82X: Maximum Tx descriptor count of 8160 (8K - 32). Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com> Co-developed-by: Alice Michael <alice.michael@intel.com> Signed-off-by: Alice Michael <alice.michael@intel.com> Signed-off-by: Paul Greenwalt <paul.greenwalt@intel.com> Acked-by: Maciej Fijalkowski <maciej.fijalkowski@intel.com> Tested-by: Rinitha S <sx.rinitha@intel.com> (A Contingent worker at Intel) Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
39 lines
1.5 KiB
C
39 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2019, Intel Corporation. */
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#ifndef _ICE_BASE_H_
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#define _ICE_BASE_H_
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#include "ice.h"
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int ice_vsi_cfg_single_rxq(struct ice_vsi *vsi, u16 q_idx);
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int ice_vsi_cfg_rxqs(struct ice_vsi *vsi);
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int __ice_vsi_get_qs(struct ice_qs_cfg *qs_cfg);
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int
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ice_vsi_ctrl_one_rx_ring(struct ice_vsi *vsi, bool ena, u16 rxq_idx, bool wait);
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int ice_vsi_wait_one_rx_ring(struct ice_vsi *vsi, bool ena, u16 rxq_idx);
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int ice_vsi_alloc_q_vectors(struct ice_vsi *vsi);
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void ice_vsi_map_rings_to_vectors(struct ice_vsi *vsi);
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void ice_vsi_free_q_vectors(struct ice_vsi *vsi);
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int ice_vsi_cfg_single_txq(struct ice_vsi *vsi, struct ice_tx_ring **tx_rings,
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u16 q_idx);
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int ice_vsi_cfg_lan_txqs(struct ice_vsi *vsi);
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int ice_vsi_cfg_xdp_txqs(struct ice_vsi *vsi);
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void ice_cfg_itr(struct ice_hw *hw, struct ice_q_vector *q_vector);
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void
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ice_cfg_txq_interrupt(struct ice_vsi *vsi, u16 txq, u16 msix_idx, u16 itr_idx);
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void
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ice_cfg_rxq_interrupt(struct ice_vsi *vsi, u16 rxq, u16 msix_idx, u16 itr_idx);
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void ice_trigger_sw_intr(struct ice_hw *hw, const struct ice_q_vector *q_vector);
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int
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ice_vsi_stop_tx_ring(struct ice_vsi *vsi, enum ice_disq_rst_src rst_src,
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u16 rel_vmvf_num, struct ice_tx_ring *ring,
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struct ice_txq_meta *txq_meta);
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void
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ice_fill_txq_meta(const struct ice_vsi *vsi, struct ice_tx_ring *ring,
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struct ice_txq_meta *txq_meta);
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int ice_qp_ena(struct ice_vsi *vsi, u16 q_idx);
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int ice_qp_dis(struct ice_vsi *vsi, u16 q_idx);
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u16 ice_calc_ts_ring_count(struct ice_tx_ring *tx_ring);
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#endif /* _ICE_BASE_H_ */
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