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4507641306
On dual complex E825, only complex 0 has functional CGU (Clock
Generation Unit), powering all the PHYs.
SBQ (Side Band Queue) destination device 'cgu' in current implementation
points to CGU on current complex and, in order to access primary CGU
from the secondary complex, the driver should use 'cgu_peer' as
a destination device in read/write CGU registers operations.
Define new 'cgu_peer' (15) as RDA (Remote Device Access) client over
SB-IOSF interface and use it as device target when accessing CGU from
secondary complex.
This problem has been identified when working on recovery clock
enablement [1]. In existing implementation for E825 devices, only PF0,
which is clock owner, is involved in CGU configuration, thus the
problem was not exposed to the user.
[1] https://lore.kernel.org/intel-wired-lan/20250905150947.871566-1-grzegorz.nitka@intel.com/
Fixes: e2193f9f9e ("ice: enable timesync operation on 2xNAC E825 devices")
Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com>
Reviewed-by: Arkadiusz Kubalewski <Arkadiusz.kubalewski@intel.com>
Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Tested-by: Rinitha S <sx.rinitha@intel.com> (A Contingent worker at Intel)
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
93 lines
1.6 KiB
C
93 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2021, Intel Corporation. */
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#ifndef _ICE_SBQ_CMD_H_
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#define _ICE_SBQ_CMD_H_
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/* This header file defines the Sideband Queue commands, error codes and
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* descriptor format. It is shared between Firmware and Software.
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*/
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/* Sideband Queue command structure and opcodes */
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enum ice_sbq_opc {
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/* Sideband Queue commands */
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ice_sbq_opc_neigh_dev_req = 0x0C00,
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ice_sbq_opc_neigh_dev_ev = 0x0C01
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};
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/* Sideband Queue descriptor. Indirect command
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* and non posted
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*/
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struct ice_sbq_cmd_desc {
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__le16 flags;
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__le16 opcode;
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__le16 datalen;
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__le16 cmd_retval;
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/* Opaque message data */
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__le32 cookie_high;
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__le32 cookie_low;
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union {
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__le16 cmd_len;
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__le16 cmpl_len;
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} param0;
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u8 reserved[6];
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__le32 addr_high;
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__le32 addr_low;
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};
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struct ice_sbq_evt_desc {
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__le16 flags;
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__le16 opcode;
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__le16 datalen;
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__le16 cmd_retval;
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u8 data[24];
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};
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enum ice_sbq_dev_id {
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ice_sbq_dev_phy_0 = 0x02,
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ice_sbq_dev_cgu = 0x06,
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ice_sbq_dev_phy_0_peer = 0x0D,
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ice_sbq_dev_cgu_peer = 0x0F,
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};
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enum ice_sbq_msg_opcode {
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ice_sbq_msg_rd = 0x00,
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ice_sbq_msg_wr = 0x01
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};
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#define ICE_SBQ_MSG_FLAGS 0x40
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#define ICE_SBQ_MSG_SBE_FBE 0x0F
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struct ice_sbq_msg_req {
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u8 dest_dev;
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u8 src_dev;
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u8 opcode;
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u8 flags;
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u8 sbe_fbe;
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u8 func_id;
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__le16 msg_addr_low;
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__le32 msg_addr_high;
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__le32 data;
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};
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struct ice_sbq_msg_cmpl {
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u8 dest_dev;
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u8 src_dev;
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u8 opcode;
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u8 flags;
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__le32 data;
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};
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/* Internal struct */
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struct ice_sbq_msg_input {
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u8 dest_dev;
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u8 opcode;
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u16 msg_addr_low;
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u32 msg_addr_high;
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u32 data;
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};
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#endif /* _ICE_SBQ_CMD_H_ */
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