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The PPE hardware counters maintain counters for packets handled by the various functional blocks of PPE. They help in tracing the packets passed through PPE and debugging any packet drops. The counters displayed by this debugfs file are ones that are common for all Ethernet ports, and they do not include the counters that are specific for a MAC port. Hence they cannot be displayed using ethtool. The per-MAC counters will be supported using "ethtool -S" along with the netdevice driver. The PPE hardware various type counters are made available through the debugfs files under directory "/sys/kernel/debug/ppe/". Signed-off-by: Luo Jie <quic_luoj@quicinc.com> Link: https://patch.msgid.link/20250818-qcom_ipq_ppe-v8-13-1d4ff641fce9@quicinc.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
240 lines
6.2 KiB
C
240 lines
6.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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/* PPE platform device probe, DTSI parser and PPE clock initializations. */
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#include <linux/clk.h>
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#include <linux/interconnect.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include "ppe.h"
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#include "ppe_config.h"
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#include "ppe_debugfs.h"
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#define PPE_PORT_MAX 8
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#define PPE_CLK_RATE 353000000
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/* ICC clocks for enabling PPE device. The avg_bw and peak_bw with value 0
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* will be updated by the clock rate of PPE.
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*/
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static const struct icc_bulk_data ppe_icc_data[] = {
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{
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.name = "ppe",
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.avg_bw = 0,
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.peak_bw = 0,
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},
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{
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.name = "ppe_cfg",
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.avg_bw = 0,
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.peak_bw = 0,
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},
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{
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.name = "qos_gen",
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.avg_bw = 6000,
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.peak_bw = 6000,
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},
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{
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.name = "timeout_ref",
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.avg_bw = 6000,
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.peak_bw = 6000,
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},
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{
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.name = "nssnoc_memnoc",
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.avg_bw = 533333,
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.peak_bw = 533333,
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},
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{
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.name = "memnoc_nssnoc",
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.avg_bw = 533333,
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.peak_bw = 533333,
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},
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{
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.name = "memnoc_nssnoc_1",
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.avg_bw = 533333,
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.peak_bw = 533333,
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},
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};
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static const struct regmap_range ppe_readable_ranges[] = {
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regmap_reg_range(0x0, 0x1ff), /* Global */
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regmap_reg_range(0x400, 0x5ff), /* LPI CSR */
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regmap_reg_range(0x1000, 0x11ff), /* GMAC0 */
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regmap_reg_range(0x1200, 0x13ff), /* GMAC1 */
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regmap_reg_range(0x1400, 0x15ff), /* GMAC2 */
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regmap_reg_range(0x1600, 0x17ff), /* GMAC3 */
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regmap_reg_range(0x1800, 0x19ff), /* GMAC4 */
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regmap_reg_range(0x1a00, 0x1bff), /* GMAC5 */
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regmap_reg_range(0xb000, 0xefff), /* PRX CSR */
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regmap_reg_range(0xf000, 0x1efff), /* IPE */
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regmap_reg_range(0x20000, 0x5ffff), /* PTX CSR */
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regmap_reg_range(0x60000, 0x9ffff), /* IPE L2 CSR */
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regmap_reg_range(0xb0000, 0xeffff), /* IPO CSR */
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regmap_reg_range(0x100000, 0x17ffff), /* IPE PC */
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regmap_reg_range(0x180000, 0x1bffff), /* PRE IPO CSR */
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regmap_reg_range(0x1d0000, 0x1dffff), /* Tunnel parser */
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regmap_reg_range(0x1e0000, 0x1effff), /* Ingress parse */
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regmap_reg_range(0x200000, 0x2fffff), /* IPE L3 */
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regmap_reg_range(0x300000, 0x3fffff), /* IPE tunnel */
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regmap_reg_range(0x400000, 0x4fffff), /* Scheduler */
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regmap_reg_range(0x500000, 0x503fff), /* XGMAC0 */
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regmap_reg_range(0x504000, 0x507fff), /* XGMAC1 */
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regmap_reg_range(0x508000, 0x50bfff), /* XGMAC2 */
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regmap_reg_range(0x50c000, 0x50ffff), /* XGMAC3 */
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regmap_reg_range(0x510000, 0x513fff), /* XGMAC4 */
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regmap_reg_range(0x514000, 0x517fff), /* XGMAC5 */
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regmap_reg_range(0x600000, 0x6fffff), /* BM */
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regmap_reg_range(0x800000, 0x9fffff), /* QM */
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regmap_reg_range(0xb00000, 0xbef800), /* EDMA */
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};
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static const struct regmap_access_table ppe_reg_table = {
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.yes_ranges = ppe_readable_ranges,
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.n_yes_ranges = ARRAY_SIZE(ppe_readable_ranges),
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};
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static const struct regmap_config regmap_config_ipq9574 = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.rd_table = &ppe_reg_table,
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.wr_table = &ppe_reg_table,
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.max_register = 0xbef800,
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.fast_io = true,
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};
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static int ppe_clock_init_and_reset(struct ppe_device *ppe_dev)
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{
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unsigned long ppe_rate = ppe_dev->clk_rate;
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struct device *dev = ppe_dev->dev;
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struct reset_control *rstc;
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struct clk_bulk_data *clks;
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struct clk *clk;
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int ret, i;
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for (i = 0; i < ppe_dev->num_icc_paths; i++) {
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ppe_dev->icc_paths[i].name = ppe_icc_data[i].name;
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ppe_dev->icc_paths[i].avg_bw = ppe_icc_data[i].avg_bw ? :
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Bps_to_icc(ppe_rate);
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/* PPE does not have an explicit peak bandwidth requirement,
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* so set the peak bandwidth to be equal to the average
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* bandwidth.
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*/
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ppe_dev->icc_paths[i].peak_bw = ppe_icc_data[i].peak_bw ? :
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Bps_to_icc(ppe_rate);
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}
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ret = devm_of_icc_bulk_get(dev, ppe_dev->num_icc_paths,
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ppe_dev->icc_paths);
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if (ret)
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return ret;
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ret = icc_bulk_set_bw(ppe_dev->num_icc_paths, ppe_dev->icc_paths);
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if (ret)
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return ret;
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/* The PPE clocks have a common parent clock. Setting the clock
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* rate of "ppe" ensures the clock rate of all PPE clocks is
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* configured to the same rate.
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*/
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clk = devm_clk_get(dev, "ppe");
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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ret = clk_set_rate(clk, ppe_rate);
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if (ret)
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return ret;
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ret = devm_clk_bulk_get_all_enabled(dev, &clks);
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if (ret < 0)
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return ret;
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/* Reset the PPE. */
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rstc = devm_reset_control_get_exclusive(dev, NULL);
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if (IS_ERR(rstc))
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return PTR_ERR(rstc);
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ret = reset_control_assert(rstc);
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if (ret)
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return ret;
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/* The delay 10 ms of assert is necessary for resetting PPE. */
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usleep_range(10000, 11000);
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return reset_control_deassert(rstc);
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}
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static int qcom_ppe_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct ppe_device *ppe_dev;
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void __iomem *base;
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int ret, num_icc;
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num_icc = ARRAY_SIZE(ppe_icc_data);
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ppe_dev = devm_kzalloc(dev, struct_size(ppe_dev, icc_paths, num_icc),
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GFP_KERNEL);
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if (!ppe_dev)
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return -ENOMEM;
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return dev_err_probe(dev, PTR_ERR(base), "PPE ioremap failed\n");
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ppe_dev->regmap = devm_regmap_init_mmio(dev, base, ®map_config_ipq9574);
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if (IS_ERR(ppe_dev->regmap))
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return dev_err_probe(dev, PTR_ERR(ppe_dev->regmap),
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"PPE initialize regmap failed\n");
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ppe_dev->dev = dev;
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ppe_dev->clk_rate = PPE_CLK_RATE;
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ppe_dev->num_ports = PPE_PORT_MAX;
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ppe_dev->num_icc_paths = num_icc;
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ret = ppe_clock_init_and_reset(ppe_dev);
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if (ret)
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return dev_err_probe(dev, ret, "PPE clock config failed\n");
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ret = ppe_hw_config(ppe_dev);
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if (ret)
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return dev_err_probe(dev, ret, "PPE HW config failed\n");
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ppe_debugfs_setup(ppe_dev);
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platform_set_drvdata(pdev, ppe_dev);
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return 0;
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}
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static void qcom_ppe_remove(struct platform_device *pdev)
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{
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struct ppe_device *ppe_dev;
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ppe_dev = platform_get_drvdata(pdev);
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ppe_debugfs_teardown(ppe_dev);
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}
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static const struct of_device_id qcom_ppe_of_match[] = {
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{ .compatible = "qcom,ipq9574-ppe" },
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{}
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};
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MODULE_DEVICE_TABLE(of, qcom_ppe_of_match);
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static struct platform_driver qcom_ppe_driver = {
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.driver = {
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.name = "qcom_ppe",
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.of_match_table = qcom_ppe_of_match,
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},
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.probe = qcom_ppe_probe,
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.remove = qcom_ppe_remove,
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};
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module_platform_driver(qcom_ppe_driver);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("Qualcomm Technologies, Inc. IPQ PPE driver");
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