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Configure the selected queues to map with an Ethernet DMA ring for the packet to receive on ARM cores. As default initialization, all queues assigned to CPU port 0 are mapped to the EDMA ring 0. This configuration is later updated during Ethernet DMA initialization. Signed-off-by: Luo Jie <quic_luoj@quicinc.com> Link: https://patch.msgid.link/20250818-qcom_ipq_ppe-v8-11-1d4ff641fce9@quicinc.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
318 lines
11 KiB
C
318 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only
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*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#ifndef __PPE_CONFIG_H__
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#define __PPE_CONFIG_H__
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#include <linux/types.h>
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#include "ppe.h"
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/* There are different table index ranges for configuring queue base ID of
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* the destination port, CPU code and service code.
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*/
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#define PPE_QUEUE_BASE_DEST_PORT 0
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#define PPE_QUEUE_BASE_CPU_CODE 1024
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#define PPE_QUEUE_BASE_SERVICE_CODE 2048
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#define PPE_QUEUE_INTER_PRI_NUM 16
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#define PPE_QUEUE_HASH_NUM 256
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/* The service code is used by EDMA port to transmit packet to PPE. */
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#define PPE_EDMA_SC_BYPASS_ID 1
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/* The PPE RSS hash configured for IPv4 and IPv6 packet separately. */
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#define PPE_RSS_HASH_MODE_IPV4 BIT(0)
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#define PPE_RSS_HASH_MODE_IPV6 BIT(1)
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#define PPE_RSS_HASH_IP_LENGTH 4
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#define PPE_RSS_HASH_TUPLES 5
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/* PPE supports 300 queues, each bit presents as one queue. */
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#define PPE_RING_TO_QUEUE_BITMAP_WORD_CNT 10
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/**
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* enum ppe_scheduler_frame_mode - PPE scheduler frame mode.
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* @PPE_SCH_WITH_IPG_PREAMBLE_FRAME_CRC: The scheduled frame includes IPG,
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* preamble, Ethernet packet and CRC.
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* @PPE_SCH_WITH_FRAME_CRC: The scheduled frame includes Ethernet frame and CRC
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* excluding IPG and preamble.
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* @PPE_SCH_WITH_L3_PAYLOAD: The scheduled frame includes layer 3 packet data.
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*/
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enum ppe_scheduler_frame_mode {
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PPE_SCH_WITH_IPG_PREAMBLE_FRAME_CRC = 0,
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PPE_SCH_WITH_FRAME_CRC = 1,
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PPE_SCH_WITH_L3_PAYLOAD = 2,
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};
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/**
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* struct ppe_scheduler_cfg - PPE scheduler configuration.
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* @flow_id: PPE flow ID.
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* @pri: Scheduler priority.
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* @drr_node_id: Node ID for scheduled traffic.
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* @drr_node_wt: Weight for scheduled traffic.
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* @unit_is_packet: Packet based or byte based unit for scheduled traffic.
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* @frame_mode: Packet mode to be scheduled.
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*
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* PPE scheduler supports commit rate and exceed rate configurations.
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*/
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struct ppe_scheduler_cfg {
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int flow_id;
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int pri;
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int drr_node_id;
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int drr_node_wt;
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bool unit_is_packet;
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enum ppe_scheduler_frame_mode frame_mode;
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};
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/**
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* enum ppe_resource_type - PPE resource type.
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* @PPE_RES_UCAST: Unicast queue resource.
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* @PPE_RES_MCAST: Multicast queue resource.
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* @PPE_RES_L0_NODE: Level 0 for queue based node resource.
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* @PPE_RES_L1_NODE: Level 1 for flow based node resource.
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* @PPE_RES_FLOW_ID: Flow based node resource.
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*/
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enum ppe_resource_type {
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PPE_RES_UCAST,
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PPE_RES_MCAST,
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PPE_RES_L0_NODE,
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PPE_RES_L1_NODE,
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PPE_RES_FLOW_ID,
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};
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/**
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* struct ppe_queue_ucast_dest - PPE unicast queue destination.
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* @src_profile: Source profile.
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* @service_code_en: Enable service code to map the queue base ID.
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* @service_code: Service code.
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* @cpu_code_en: Enable CPU code to map the queue base ID.
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* @cpu_code: CPU code.
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* @dest_port: destination port.
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*
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* PPE egress queue ID is decided by the service code if enabled, otherwise
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* by the CPU code if enabled, or by destination port if both service code
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* and CPU code are disabled.
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*/
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struct ppe_queue_ucast_dest {
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int src_profile;
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bool service_code_en;
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int service_code;
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bool cpu_code_en;
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int cpu_code;
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int dest_port;
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};
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/* Hardware bitmaps for bypassing features of the ingress packet. */
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enum ppe_sc_ingress_type {
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PPE_SC_BYPASS_INGRESS_VLAN_TAG_FMT_CHECK = 0,
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PPE_SC_BYPASS_INGRESS_VLAN_MEMBER_CHECK = 1,
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PPE_SC_BYPASS_INGRESS_VLAN_TRANSLATE = 2,
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PPE_SC_BYPASS_INGRESS_MY_MAC_CHECK = 3,
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PPE_SC_BYPASS_INGRESS_DIP_LOOKUP = 4,
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PPE_SC_BYPASS_INGRESS_FLOW_LOOKUP = 5,
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PPE_SC_BYPASS_INGRESS_FLOW_ACTION = 6,
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PPE_SC_BYPASS_INGRESS_ACL = 7,
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PPE_SC_BYPASS_INGRESS_FAKE_MAC_HEADER = 8,
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PPE_SC_BYPASS_INGRESS_SERVICE_CODE = 9,
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PPE_SC_BYPASS_INGRESS_WRONG_PKT_FMT_L2 = 10,
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PPE_SC_BYPASS_INGRESS_WRONG_PKT_FMT_L3_IPV4 = 11,
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PPE_SC_BYPASS_INGRESS_WRONG_PKT_FMT_L3_IPV6 = 12,
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PPE_SC_BYPASS_INGRESS_WRONG_PKT_FMT_L4 = 13,
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PPE_SC_BYPASS_INGRESS_FLOW_SERVICE_CODE = 14,
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PPE_SC_BYPASS_INGRESS_ACL_SERVICE_CODE = 15,
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PPE_SC_BYPASS_INGRESS_FAKE_L2_PROTO = 16,
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PPE_SC_BYPASS_INGRESS_PPPOE_TERMINATION = 17,
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PPE_SC_BYPASS_INGRESS_DEFAULT_VLAN = 18,
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PPE_SC_BYPASS_INGRESS_DEFAULT_PCP = 19,
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PPE_SC_BYPASS_INGRESS_VSI_ASSIGN = 20,
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/* Values 21-23 are not specified by hardware. */
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PPE_SC_BYPASS_INGRESS_VLAN_ASSIGN_FAIL = 24,
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PPE_SC_BYPASS_INGRESS_SOURCE_GUARD = 25,
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PPE_SC_BYPASS_INGRESS_MRU_MTU_CHECK = 26,
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PPE_SC_BYPASS_INGRESS_FLOW_SRC_CHECK = 27,
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PPE_SC_BYPASS_INGRESS_FLOW_QOS = 28,
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/* This must be last as it determines the size of the BITMAP. */
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PPE_SC_BYPASS_INGRESS_SIZE,
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};
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/* Hardware bitmaps for bypassing features of the egress packet. */
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enum ppe_sc_egress_type {
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PPE_SC_BYPASS_EGRESS_VLAN_MEMBER_CHECK = 0,
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PPE_SC_BYPASS_EGRESS_VLAN_TRANSLATE = 1,
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PPE_SC_BYPASS_EGRESS_VLAN_TAG_FMT_CTRL = 2,
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PPE_SC_BYPASS_EGRESS_FDB_LEARN = 3,
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PPE_SC_BYPASS_EGRESS_FDB_REFRESH = 4,
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PPE_SC_BYPASS_EGRESS_L2_SOURCE_SECURITY = 5,
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PPE_SC_BYPASS_EGRESS_MANAGEMENT_FWD = 6,
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PPE_SC_BYPASS_EGRESS_BRIDGING_FWD = 7,
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PPE_SC_BYPASS_EGRESS_IN_STP_FLTR = 8,
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PPE_SC_BYPASS_EGRESS_EG_STP_FLTR = 9,
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PPE_SC_BYPASS_EGRESS_SOURCE_FLTR = 10,
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PPE_SC_BYPASS_EGRESS_POLICER = 11,
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PPE_SC_BYPASS_EGRESS_L2_PKT_EDIT = 12,
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PPE_SC_BYPASS_EGRESS_L3_PKT_EDIT = 13,
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PPE_SC_BYPASS_EGRESS_ACL_POST_ROUTING_CHECK = 14,
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PPE_SC_BYPASS_EGRESS_PORT_ISOLATION = 15,
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PPE_SC_BYPASS_EGRESS_PRE_ACL_QOS = 16,
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PPE_SC_BYPASS_EGRESS_POST_ACL_QOS = 17,
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PPE_SC_BYPASS_EGRESS_DSCP_QOS = 18,
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PPE_SC_BYPASS_EGRESS_PCP_QOS = 19,
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PPE_SC_BYPASS_EGRESS_PREHEADER_QOS = 20,
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PPE_SC_BYPASS_EGRESS_FAKE_MAC_DROP = 21,
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PPE_SC_BYPASS_EGRESS_TUNL_CONTEXT = 22,
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PPE_SC_BYPASS_EGRESS_FLOW_POLICER = 23,
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/* This must be last as it determines the size of the BITMAP. */
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PPE_SC_BYPASS_EGRESS_SIZE,
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};
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/* Hardware bitmaps for bypassing counter of packet. */
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enum ppe_sc_counter_type {
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PPE_SC_BYPASS_COUNTER_RX_VLAN = 0,
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PPE_SC_BYPASS_COUNTER_RX = 1,
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PPE_SC_BYPASS_COUNTER_TX_VLAN = 2,
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PPE_SC_BYPASS_COUNTER_TX = 3,
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/* This must be last as it determines the size of the BITMAP. */
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PPE_SC_BYPASS_COUNTER_SIZE,
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};
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/* Hardware bitmaps for bypassing features of tunnel packet. */
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enum ppe_sc_tunnel_type {
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PPE_SC_BYPASS_TUNNEL_SERVICE_CODE = 0,
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PPE_SC_BYPASS_TUNNEL_TUNNEL_HANDLE = 1,
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PPE_SC_BYPASS_TUNNEL_L3_IF_CHECK = 2,
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PPE_SC_BYPASS_TUNNEL_VLAN_CHECK = 3,
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PPE_SC_BYPASS_TUNNEL_DMAC_CHECK = 4,
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PPE_SC_BYPASS_TUNNEL_UDP_CSUM_0_CHECK = 5,
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PPE_SC_BYPASS_TUNNEL_TBL_DE_ACCE_CHECK = 6,
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PPE_SC_BYPASS_TUNNEL_PPPOE_MC_TERM_CHECK = 7,
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PPE_SC_BYPASS_TUNNEL_TTL_EXCEED_CHECK = 8,
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PPE_SC_BYPASS_TUNNEL_MAP_SRC_CHECK = 9,
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PPE_SC_BYPASS_TUNNEL_MAP_DST_CHECK = 10,
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PPE_SC_BYPASS_TUNNEL_LPM_DST_LOOKUP = 11,
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PPE_SC_BYPASS_TUNNEL_LPM_LOOKUP = 12,
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PPE_SC_BYPASS_TUNNEL_WRONG_PKT_FMT_L2 = 13,
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PPE_SC_BYPASS_TUNNEL_WRONG_PKT_FMT_L3_IPV4 = 14,
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PPE_SC_BYPASS_TUNNEL_WRONG_PKT_FMT_L3_IPV6 = 15,
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PPE_SC_BYPASS_TUNNEL_WRONG_PKT_FMT_L4 = 16,
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PPE_SC_BYPASS_TUNNEL_WRONG_PKT_FMT_TUNNEL = 17,
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/* Values 18-19 are not specified by hardware. */
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PPE_SC_BYPASS_TUNNEL_PRE_IPO = 20,
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/* This must be last as it determines the size of the BITMAP. */
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PPE_SC_BYPASS_TUNNEL_SIZE,
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};
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/**
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* struct ppe_sc_bypass - PPE service bypass bitmaps
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* @ingress: Bitmap of features that can be bypassed on the ingress packet.
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* @egress: Bitmap of features that can be bypassed on the egress packet.
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* @counter: Bitmap of features that can be bypassed on the counter type.
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* @tunnel: Bitmap of features that can be bypassed on the tunnel packet.
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*/
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struct ppe_sc_bypass {
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DECLARE_BITMAP(ingress, PPE_SC_BYPASS_INGRESS_SIZE);
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DECLARE_BITMAP(egress, PPE_SC_BYPASS_EGRESS_SIZE);
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DECLARE_BITMAP(counter, PPE_SC_BYPASS_COUNTER_SIZE);
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DECLARE_BITMAP(tunnel, PPE_SC_BYPASS_TUNNEL_SIZE);
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};
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/**
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* struct ppe_sc_cfg - PPE service code configuration.
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* @dest_port_valid: Generate destination port or not.
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* @dest_port: Destination port ID.
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* @bitmaps: Bitmap of bypass features.
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* @is_src: Destination port acts as source port, packet sent to CPU.
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* @next_service_code: New service code generated.
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* @eip_field_update_bitmap: Fields updated as actions taken for EIP.
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* @eip_hw_service: Selected hardware functions for EIP.
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* @eip_offset_sel: Packet offset selection, using packet's layer 4 offset
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* or using packet's layer 3 offset for EIP.
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*
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* Service code is generated during the packet passing through PPE.
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*/
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struct ppe_sc_cfg {
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bool dest_port_valid;
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int dest_port;
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struct ppe_sc_bypass bitmaps;
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bool is_src;
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int next_service_code;
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int eip_field_update_bitmap;
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int eip_hw_service;
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int eip_offset_sel;
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};
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/**
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* enum ppe_action_type - PPE action of the received packet.
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* @PPE_ACTION_FORWARD: Packet forwarded per L2/L3 process.
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* @PPE_ACTION_DROP: Packet dropped by PPE.
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* @PPE_ACTION_COPY_TO_CPU: Packet copied to CPU port per multicast queue.
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* @PPE_ACTION_REDIRECT_TO_CPU: Packet redirected to CPU port per unicast queue.
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*/
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enum ppe_action_type {
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PPE_ACTION_FORWARD = 0,
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PPE_ACTION_DROP = 1,
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PPE_ACTION_COPY_TO_CPU = 2,
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PPE_ACTION_REDIRECT_TO_CPU = 3,
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};
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/**
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* struct ppe_rss_hash_cfg - PPE RSS hash configuration.
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* @hash_mask: Mask of the generated hash value.
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* @hash_fragment_mode: Hash generation mode for the first fragment of TCP,
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* UDP and UDP-Lite packets, to use either 3 tuple or 5 tuple for RSS hash
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* key computation.
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* @hash_seed: Seed to generate RSS hash.
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* @hash_sip_mix: Source IP selection.
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* @hash_dip_mix: Destination IP selection.
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* @hash_protocol_mix: Protocol selection.
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* @hash_sport_mix: Source L4 port selection.
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* @hash_dport_mix: Destination L4 port selection.
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* @hash_fin_inner: RSS hash value first selection.
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* @hash_fin_outer: RSS hash value second selection.
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*
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* PPE RSS hash value is generated for the packet based on the RSS hash
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* configured.
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*/
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struct ppe_rss_hash_cfg {
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u32 hash_mask;
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bool hash_fragment_mode;
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u32 hash_seed;
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u8 hash_sip_mix[PPE_RSS_HASH_IP_LENGTH];
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u8 hash_dip_mix[PPE_RSS_HASH_IP_LENGTH];
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u8 hash_protocol_mix;
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u8 hash_sport_mix;
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u8 hash_dport_mix;
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u8 hash_fin_inner[PPE_RSS_HASH_TUPLES];
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u8 hash_fin_outer[PPE_RSS_HASH_TUPLES];
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};
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int ppe_hw_config(struct ppe_device *ppe_dev);
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int ppe_queue_scheduler_set(struct ppe_device *ppe_dev,
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int node_id, bool flow_level, int port,
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struct ppe_scheduler_cfg scheduler_cfg);
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int ppe_queue_ucast_base_set(struct ppe_device *ppe_dev,
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struct ppe_queue_ucast_dest queue_dst,
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int queue_base,
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int profile_id);
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int ppe_queue_ucast_offset_pri_set(struct ppe_device *ppe_dev,
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int profile_id,
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int priority,
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int queue_offset);
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int ppe_queue_ucast_offset_hash_set(struct ppe_device *ppe_dev,
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int profile_id,
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int rss_hash,
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int queue_offset);
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int ppe_port_resource_get(struct ppe_device *ppe_dev, int port,
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enum ppe_resource_type type,
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int *res_start, int *res_end);
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int ppe_sc_config_set(struct ppe_device *ppe_dev, int sc,
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struct ppe_sc_cfg cfg);
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int ppe_counter_enable_set(struct ppe_device *ppe_dev, int port);
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int ppe_rss_hash_config_set(struct ppe_device *ppe_dev, int mode,
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struct ppe_rss_hash_cfg hash_cfg);
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int ppe_ring_queue_map_set(struct ppe_device *ppe_dev,
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int ring_id,
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u32 *queue_map);
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#endif
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