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TX head write-back mode is supported on AML devices. When it is enabled, the hardware no longer writes the descriptors DD one by one, but write back pointer of completion descriptor to the head_wb address. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> Link: https://patch.msgid.link/20251023014538.12644-3-jiawenwu@trustnetic.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
130 lines
5.0 KiB
C
130 lines
5.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2015 - 2025 Beijing WangXun Technology Co., Ltd. */
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#ifndef _WX_VF_H_
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#define _WX_VF_H_
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/* Control registers */
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#define WX_VF_MAX_RING_NUMS 8
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#define WX_VX_PF_BME 0x4B8
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#define WX_VF_BME_ENABLE BIT(0)
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#define WX_VXSTATUS 0x4
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#define WX_VXCTRL 0x8
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#define WX_VXCTRL_RST BIT(0)
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#define WX_VXMRQC 0x78
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#define WX_VXMRQC_PSR_L4HDR BIT(0)
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#define WX_VXMRQC_PSR_L3HDR BIT(1)
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#define WX_VXMRQC_PSR_L2HDR BIT(2)
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#define WX_VXMRQC_PSR_TUNHDR BIT(3)
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#define WX_VXMRQC_PSR_TUNMAC BIT(4)
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#define WX_VXMRQC_PSR_MASK GENMASK(5, 1)
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#define WX_VXMRQC_PSR(f) FIELD_PREP(GENMASK(5, 1), f)
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#define WX_VXMRQC_RSS_HASH(f) FIELD_PREP(GENMASK(15, 13), f)
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#define WX_VXMRQC_RSS_MASK GENMASK(31, 16)
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#define WX_VXMRQC_RSS(f) FIELD_PREP(GENMASK(31, 16), f)
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#define WX_VXMRQC_RSS_ALG_IPV4_TCP BIT(0)
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#define WX_VXMRQC_RSS_ALG_IPV4 BIT(1)
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#define WX_VXMRQC_RSS_ALG_IPV6 BIT(4)
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#define WX_VXMRQC_RSS_ALG_IPV6_TCP BIT(5)
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#define WX_VXMRQC_RSS_EN BIT(8)
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#define WX_VXRSSRK(i) (0x80 + ((i) * 4)) /* i=[0,9] */
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#define WX_VXRETA(i) (0xC0 + ((i) * 4)) /* i=[0,15] */
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/* Interrupt registers */
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#define WX_VXICR 0x100
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#define WX_VXIMS 0x108
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#define WX_VXIMC 0x10C
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#define WX_VF_IRQ_CLEAR_MASK 7
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#define WX_VF_MAX_TX_QUEUES 4
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#define WX_VF_MAX_RX_QUEUES 4
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#define WX_VXITR(i) (0x200 + (4 * (i))) /* i=[0,1] */
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#define WX_VXITR_MASK GENMASK(8, 0)
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#define WX_VXITR_CNT_WDIS BIT(31)
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#define WX_VXIVAR_MISC 0x260
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#define WX_VXIVAR(i) (0x240 + (4 * (i))) /* i=[0,3] */
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#define wx_conf_size(v, mwidth, uwidth) ({ \
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typeof(v) _v = (v); \
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(_v == 2 << (mwidth) ? 0 : _v >> (uwidth)); \
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})
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#define wx_buf_len(v) wx_conf_size(v, 13, 7)
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#define wx_hdr_sz(v) wx_conf_size(v, 10, 6)
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#define wx_buf_sz(v) wx_conf_size(v, 14, 10)
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#define wx_pkt_thresh(v) wx_conf_size(v, 4, 0)
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#define WX_RX_HDR_SIZE 256
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#define WX_RX_BUF_SIZE 2048
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#define WX_RXBUFFER_2048 (2048)
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#define WX_RXBUFFER_3072 3072
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/* Receive Path */
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#define WX_VXRDBAL(r) (0x1000 + (0x40 * (r)))
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#define WX_VXRDBAH(r) (0x1004 + (0x40 * (r)))
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#define WX_VXRDT(r) (0x1008 + (0x40 * (r)))
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#define WX_VXRDH(r) (0x100C + (0x40 * (r)))
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#define WX_VXRXDCTL(r) (0x1010 + (0x40 * (r)))
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#define WX_VXRXDCTL_ENABLE BIT(0)
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#define WX_VXRXDCTL_BUFLEN_MASK GENMASK(6, 1)
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#define WX_VXRXDCTL_BUFLEN(f) FIELD_PREP(GENMASK(6, 1), f)
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#define WX_VXRXDCTL_BUFSZ_MASK GENMASK(11, 8)
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#define WX_VXRXDCTL_BUFSZ(f) FIELD_PREP(GENMASK(11, 8), f)
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#define WX_VXRXDCTL_HDRSZ_MASK GENMASK(15, 12)
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#define WX_VXRXDCTL_HDRSZ(f) FIELD_PREP(GENMASK(15, 12), f)
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#define WX_VXRXDCTL_DESC_MERGE BIT(19)
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#define WX_VXRXDCTL_RSCMAX_MASK GENMASK(24, 23)
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#define WX_VXRXDCTL_RSCMAX(f) FIELD_PREP(GENMASK(24, 23), f)
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#define WX_VXRXDCTL_RSCEN BIT(29)
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#define WX_VXRXDCTL_DROP BIT(30)
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#define WX_VXRXDCTL_VLAN BIT(31)
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/* Transimit Path */
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#define WX_VXTDBAL(r) (0x3000 + (0x40 * (r)))
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#define WX_VXTDBAH(r) (0x3004 + (0x40 * (r)))
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#define WX_VXTDT(r) (0x3008 + (0x40 * (r)))
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#define WX_VXTDH(r) (0x300C + (0x40 * (r)))
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#define WX_VXTXDCTL(r) (0x3010 + (0x40 * (r)))
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#define WX_VXTXDCTL_ENABLE BIT(0)
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#define WX_VXTXDCTL_BUFLEN(f) FIELD_PREP(GENMASK(6, 1), f)
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#define WX_VXTXDCTL_PTHRESH(f) FIELD_PREP(GENMASK(11, 8), f)
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#define WX_VXTXDCTL_WTHRESH(f) FIELD_PREP(GENMASK(22, 16), f)
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#define WX_VXTXDCTL_FLUSH BIT(26)
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#define WX_VXTXDCTL_HEAD_WB BIT(27)
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#define WX_VXTXD_HEAD_ADDRL(r) (0x3028 + (0x40 * (r)))
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#define WX_VXTXD_HEAD_ADDRH(r) (0x302C + (0x40 * (r)))
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#define WX_PFLINK_STATUS(g) FIELD_GET(BIT(0), g)
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#define WX_PFLINK_SPEED(g) FIELD_GET(GENMASK(31, 1), g)
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#define WX_VXSTATUS_SPEED(g) FIELD_GET(GENMASK(4, 1), g)
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struct wx_link_reg_fields {
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u32 mac_type;
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u32 bit0_f;
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u32 bit1_f;
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u32 bit2_f;
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u32 bit3_f;
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u32 bit4_f;
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};
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void wx_init_hw_vf(struct wx *wx);
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int wx_reset_hw_vf(struct wx *wx);
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void wx_get_mac_addr_vf(struct wx *wx, u8 *mac_addr);
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void wx_stop_adapter_vf(struct wx *wx);
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int wx_get_fw_version_vf(struct wx *wx);
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int wx_set_rar_vf(struct wx *wx, u32 index, u8 *addr, u32 enable_addr);
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int wx_update_mc_addr_list_vf(struct wx *wx, struct net_device *netdev);
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int wx_set_uc_addr_vf(struct wx *wx, u32 index, u8 *addr);
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int wx_rlpml_set_vf(struct wx *wx, u16 max_size);
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int wx_negotiate_api_version(struct wx *wx, int api);
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int wx_get_queues_vf(struct wx *wx, u32 *num_tcs, u32 *default_tc);
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int wx_update_xcast_mode_vf(struct wx *wx, int xcast_mode);
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int wx_get_link_state_vf(struct wx *wx, u16 *link_state);
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int wx_set_vfta_vf(struct wx *wx, u32 vlan, u32 vind, bool vlan_on,
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bool vlvf_bypass);
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int wx_check_mac_link_vf(struct wx *wx);
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#endif /* _WX_VF_H_ */
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