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45a8d350e7
Convert the Marvell CP110 System Controller binding to DT schema format. There's not any specific compatible for the whole block which is a separate problem, so just the child nodes are documented. Only the pinctrl and clock child nodes need to be converted as the GPIO node already has a schema. Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://patch.msgid.link/20251022165509.3917655-2-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
71 lines
1.9 KiB
YAML
71 lines
1.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/marvell,cp110-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Marvell Armada CP110 System Controller Clocks
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maintainers:
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- Gregory Clement <gregory.clement@bootlin.com>
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- Miquel Raynal <miquel.raynal@bootlin.com>
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description: >
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The CP110 is one of the two core HW blocks of the Marvell Armada 7K/8K/931x
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SoCs. It contains system controllers, which provide several registers giving
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access to numerous features: clocks, pin-muxing and many other SoC
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configuration items.
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properties:
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compatible:
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const: marvell,cp110-clock
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"#clock-cells":
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const: 2
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description: >
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The first cell must be 0 or 1. 0 for the core clocks and 1 for the
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gateable clocks. The second cell identifies the particular core clock or
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gateable clocks.
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The following clocks are available:
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- Core clocks
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- 0 0 APLL
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- 0 1 PPv2 core
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- 0 2 EIP
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- 0 3 Core
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- 0 4 NAND core
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- 0 5 SDIO core
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- Gateable clocks
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- 1 0 Audio
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- 1 1 Comm Unit
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- 1 2 NAND
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- 1 3 PPv2
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- 1 4 SDIO
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- 1 5 MG Domain
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- 1 6 MG Core
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- 1 7 XOR1
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- 1 8 XOR0
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- 1 9 GOP DP
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- 1 11 PCIe x1 0
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- 1 12 PCIe x1 1
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- 1 13 PCIe x4
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- 1 14 PCIe / XOR
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- 1 15 SATA
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- 1 16 SATA USB
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- 1 17 Main
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- 1 18 SD/MMC/GOP
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- 1 21 Slow IO (SPI, NOR, BootROM, I2C, UART)
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- 1 22 USB3H0
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- 1 23 USB3H1
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- 1 24 USB3 Device
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- 1 25 EIP150
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- 1 26 EIP197
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required:
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- compatible
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- "#clock-cells"
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additionalProperties: false
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