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9be5c47908
On a vast majority of Qualcomm chipsets DisplayPort controller can support several MST streams (up to 4x). To support MST these chipsets use up to 4 stream pixel clocks for the DisplayPort controller and several extra register regions. Expand corresponding region and clock bindings for these platforms and fix example schema files to follow updated bindings. Note: On chipsets that support MST, the number of streams supported can vary between controllers. For example, SA8775P supports 4 MST streams on mdss_dp0 but only 2 streams on mdss_dp1. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/672585/ Link: https://lore.kernel.org/r/20250903-dp_mst_bindings-v8-7-7526f0311eaa@oss.qualcomm.com
445 lines
13 KiB
YAML
445 lines
13 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/qcom,sc7280-mdss.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SC7280 Display MDSS
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maintainers:
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- Krishna Manikandan <quic_mkrishn@quicinc.com>
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description:
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Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates
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sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
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bindings of MDSS are mentioned for SC7280.
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$ref: /schemas/display/msm/mdss-common.yaml#
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properties:
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compatible:
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const: qcom,sc7280-mdss
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clocks:
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items:
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- description: Display AHB clock from gcc
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- description: Display AHB clock from dispcc
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- description: Display core clock
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clock-names:
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items:
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- const: iface
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- const: ahb
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- const: core
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iommus:
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maxItems: 1
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interconnects:
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items:
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- description: Interconnect path from mdp0 port to the data bus
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- description: Interconnect path from CPU to the reg bus
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interconnect-names:
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items:
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- const: mdp0-mem
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- const: cpu-cfg
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patternProperties:
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"^display-controller@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: qcom,sc7280-dpu
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"^displayport-controller@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: qcom,sc7280-dp
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"^dsi@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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items:
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- const: qcom,sc7280-dsi-ctrl
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- const: qcom,mdss-dsi-ctrl
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"^edp@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: qcom,sc7280-edp
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"^phy@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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enum:
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- qcom,sc7280-dsi-phy-7nm
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- qcom,sc7280-edp-phy
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required:
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- compatible
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,dispcc-sc7280.h>
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#include <dt-bindings/clock/qcom,gcc-sc7280.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interconnect/qcom,sc7280.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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display-subsystem@ae00000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "qcom,sc7280-mdss";
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reg = <0xae00000 0x1000>;
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reg-names = "mdss";
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power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
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clocks = <&gcc GCC_DISP_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>;
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clock-names = "iface",
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"ahb",
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"core";
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>,
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<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_DISPLAY_CFG>;
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interconnect-names = "mdp0-mem",
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"cpu-cfg";
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iommus = <&apps_smmu 0x900 0x402>;
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ranges;
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display-controller@ae01000 {
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compatible = "qcom,sc7280-dpu";
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reg = <0x0ae01000 0x8f000>,
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<0x0aeb0000 0x2008>;
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reg-names = "mdp", "vbif";
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clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
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<&gcc GCC_DISP_SF_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>,
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<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
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clock-names = "bus",
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"nrt_bus",
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"iface",
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"lut",
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"core",
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"vsync";
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interrupt-parent = <&mdss>;
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interrupts = <0>;
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power-domains = <&rpmhpd SC7280_CX>;
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operating-points-v2 = <&mdp_opp_table>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dpu_intf1_out: endpoint {
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remote-endpoint = <&dsi0_in>;
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};
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};
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port@1 {
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reg = <1>;
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dpu_intf5_out: endpoint {
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remote-endpoint = <&edp_in>;
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};
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};
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port@2 {
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reg = <2>;
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dpu_intf0_out: endpoint {
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remote-endpoint = <&dp_in>;
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};
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};
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};
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};
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dsi@ae94000 {
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compatible = "qcom,sc7280-dsi-ctrl", "qcom,mdss-dsi-ctrl";
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reg = <0x0ae94000 0x400>;
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reg-names = "dsi_ctrl";
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interrupt-parent = <&mdss>;
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interrupts = <4>;
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clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
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<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
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<&dispcc DISP_CC_MDSS_ESC0_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&gcc GCC_DISP_HF_AXI_CLK>;
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clock-names = "byte",
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"byte_intf",
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"pixel",
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"core",
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"iface",
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"bus";
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assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
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assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>;
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operating-points-v2 = <&dsi_opp_table>;
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power-domains = <&rpmhpd SC7280_CX>;
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phys = <&mdss_dsi_phy>;
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phy-names = "dsi";
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#address-cells = <1>;
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#size-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dsi0_in: endpoint {
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remote-endpoint = <&dpu_intf1_out>;
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};
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};
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port@1 {
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reg = <1>;
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dsi0_out: endpoint {
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};
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};
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};
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dsi_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-187500000 {
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opp-hz = /bits/ 64 <187500000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-300000000 {
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opp-hz = /bits/ 64 <300000000>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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opp-358000000 {
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opp-hz = /bits/ 64 <358000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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};
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};
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mdss_dsi_phy: phy@ae94400 {
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compatible = "qcom,sc7280-dsi-phy-7nm";
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reg = <0x0ae94400 0x200>,
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<0x0ae94600 0x280>,
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<0x0ae94900 0x280>;
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reg-names = "dsi_phy",
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"dsi_phy_lane",
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"dsi_pll";
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#clock-cells = <1>;
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#phy-cells = <0>;
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "iface", "ref";
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vdds-supply = <&vreg_dsi_supply>;
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};
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edp@aea0000 {
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compatible = "qcom,sc7280-edp";
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pinctrl-names = "default";
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pinctrl-0 = <&edp_hot_plug_det>;
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reg = <0xaea0000 0x200>,
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<0xaea0200 0x200>,
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<0xaea0400 0xc00>,
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<0xaea1000 0x400>,
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<0xaea1400 0x400>;
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interrupt-parent = <&mdss>;
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interrupts = <14>;
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
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<&dispcc DISP_CC_MDSS_EDP_LINK_CLK>,
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<&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>;
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clock-names = "core_iface",
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"core_aux",
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"ctrl_link",
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"ctrl_link_iface",
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"stream_pixel";
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assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
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assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
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phys = <&mdss_edp_phy>;
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phy-names = "dp";
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operating-points-v2 = <&edp_opp_table>;
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power-domains = <&rpmhpd SC7280_CX>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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edp_in: endpoint {
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remote-endpoint = <&dpu_intf5_out>;
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};
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};
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port@1 {
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reg = <1>;
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mdss_edp_out: endpoint { };
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};
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};
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edp_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-160000000 {
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opp-hz = /bits/ 64 <160000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-270000000 {
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opp-hz = /bits/ 64 <270000000>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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opp-540000000 {
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opp-hz = /bits/ 64 <540000000>;
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required-opps = <&rpmhpd_opp_nom>;
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};
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opp-810000000 {
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opp-hz = /bits/ 64 <810000000>;
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required-opps = <&rpmhpd_opp_nom>;
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};
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};
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};
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mdss_edp_phy: phy@aec2a00 {
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compatible = "qcom,sc7280-edp-phy";
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reg = <0xaec2a00 0x19c>,
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<0xaec2200 0xa0>,
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<0xaec2600 0xa0>,
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<0xaec2000 0x1c0>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_EDP_CLKREF_EN>;
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clock-names = "aux",
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"cfg_ahb";
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#clock-cells = <1>;
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#phy-cells = <0>;
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};
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displayport-controller@ae90000 {
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compatible = "qcom,sc7280-dp";
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reg = <0xae90000 0x200>,
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<0xae90200 0x200>,
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<0xae90400 0xc00>,
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<0xae91000 0x400>,
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<0xae91400 0x400>;
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interrupt-parent = <&mdss>;
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interrupts = <12>;
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
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<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
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<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
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clock-names = "core_iface",
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"core_aux",
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"ctrl_link",
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"ctrl_link_iface",
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"stream_pixel";
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assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
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assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
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phys = <&dp_phy>;
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phy-names = "dp";
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operating-points-v2 = <&dp_opp_table>;
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power-domains = <&rpmhpd SC7280_CX>;
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#sound-dai-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dp_in: endpoint {
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remote-endpoint = <&dpu_intf0_out>;
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};
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};
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port@1 {
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reg = <1>;
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dp_out: endpoint { };
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};
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};
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dp_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-160000000 {
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opp-hz = /bits/ 64 <160000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-270000000 {
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opp-hz = /bits/ 64 <270000000>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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opp-540000000 {
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opp-hz = /bits/ 64 <540000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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opp-810000000 {
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opp-hz = /bits/ 64 <810000000>;
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required-opps = <&rpmhpd_opp_nom>;
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};
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};
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};
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};
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...
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