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linux/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
Nicolas Frattaroli 2568b8b086 dt-bindings: gpu: mali-valhall-csf: Add shader-present nvmem cell
On the MediaTek MT8196 SoC, the bitmask for which shader cores are
present and functional is not the one in the Mali GPU's registers, but
in an external efuse.

Add the nvmem cell properties to describe such a setup, and make them
required on MT8196.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Link: https://patch.msgid.link/20251220-mt8196-shader-present-v2-1-45b1ff1dfab0@collabora.com
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2026-01-13 17:05:59 +01:00

200 lines
4.9 KiB
YAML

# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/arm,mali-valhall-csf.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Mali Valhall GPU
maintainers:
- Liviu Dudau <liviu.dudau@arm.com>
- Boris Brezillon <boris.brezillon@collabora.com>
properties:
$nodename:
pattern: '^gpu@[a-f0-9]+$'
compatible:
oneOf:
- items:
- enum:
- mediatek,mt8196-mali
- nxp,imx95-mali # G310
- rockchip,rk3588-mali
- const: arm,mali-valhall-csf # Mali Valhall GPU model/revision is fully discoverable
reg:
maxItems: 1
interrupts:
items:
- description: Job interrupt
- description: MMU interrupt
- description: GPU interrupt
interrupt-names:
items:
- const: job
- const: mmu
- const: gpu
clocks:
minItems: 1
maxItems: 3
clock-names:
minItems: 1
items:
- const: core
- enum:
- coregroup
- stacks
- const: stacks
nvmem-cells:
items:
- description: bitmask of functional shader cores
nvmem-cell-names:
items:
- const: shader-present
mali-supply: true
operating-points-v2: true
opp-table:
type: object
power-domains:
minItems: 1
maxItems: 5
power-domain-names:
minItems: 1
maxItems: 5
sram-supply: true
"#cooling-cells":
const: 2
dynamic-power-coefficient:
$ref: /schemas/types.yaml#/definitions/uint32
description:
A u32 value that represents the running time dynamic
power coefficient in units of uW/MHz/V^2. The
coefficient can either be calculated from power
measurements or derived by analysis.
The dynamic power consumption of the GPU is
proportional to the square of the Voltage (V) and
the clock frequency (f). The coefficient is used to
calculate the dynamic power as below -
Pdyn = dynamic-power-coefficient * V^2 * f
where voltage is in V, frequency is in MHz.
dma-coherent: true
required:
- compatible
- reg
- interrupts
- interrupt-names
- clocks
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
const: rockchip,rk3588-mali
then:
properties:
clocks:
minItems: 3
nvmem-cells: false
nvmem-cell-names: false
power-domains:
maxItems: 1
power-domain-names: false
required:
- mali-supply
- if:
properties:
compatible:
contains:
const: mediatek,mt8196-mali
then:
properties:
mali-supply: false
sram-supply: false
operating-points-v2: false
power-domains:
maxItems: 1
power-domain-names: false
clocks:
maxItems: 2
clock-names:
items:
- const: core
- const: stacks
required:
- nvmem-cells
- nvmem-cell-names
- power-domains
examples:
- |
#include <dt-bindings/clock/rockchip,rk3588-cru.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/rk3588-power.h>
gpu: gpu@fb000000 {
compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
reg = <0xfb000000 0x200000>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "job", "mmu", "gpu";
clock-names = "core", "coregroup", "stacks";
clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
<&cru CLK_GPU_STACKS>;
power-domains = <&power RK3588_PD_GPU>;
operating-points-v2 = <&gpu_opp_table>;
mali-supply = <&vdd_gpu_s0>;
sram-supply = <&vdd_gpu_mem_s0>;
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <675000 675000 850000>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <675000 675000 850000>;
};
};
};
- |
gpu@48000000 {
compatible = "mediatek,mt8196-mali", "arm,mali-valhall-csf";
reg = <0x48000000 0x480000>;
clocks = <&gpufreq 0>, <&gpufreq 1>;
clock-names = "core", "stacks";
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "job", "mmu", "gpu";
nvmem-cells = <&shader_present>;
nvmem-cell-names = "shader-present";
power-domains = <&gpufreq>;
};
...