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On the MediaTek MT8196 SoC, the bitmask for which shader cores are present and functional is not the one in the Mali GPU's registers, but in an external efuse. Add the nvmem cell properties to describe such a setup, and make them required on MT8196. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://patch.msgid.link/20251220-mt8196-shader-present-v2-1-45b1ff1dfab0@collabora.com Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
200 lines
4.9 KiB
YAML
200 lines
4.9 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/gpu/arm,mali-valhall-csf.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM Mali Valhall GPU
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maintainers:
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- Liviu Dudau <liviu.dudau@arm.com>
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- Boris Brezillon <boris.brezillon@collabora.com>
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properties:
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$nodename:
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pattern: '^gpu@[a-f0-9]+$'
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compatible:
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oneOf:
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- items:
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- enum:
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- mediatek,mt8196-mali
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- nxp,imx95-mali # G310
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- rockchip,rk3588-mali
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- const: arm,mali-valhall-csf # Mali Valhall GPU model/revision is fully discoverable
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reg:
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maxItems: 1
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interrupts:
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items:
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- description: Job interrupt
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- description: MMU interrupt
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- description: GPU interrupt
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interrupt-names:
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items:
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- const: job
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- const: mmu
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- const: gpu
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clocks:
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minItems: 1
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maxItems: 3
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clock-names:
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minItems: 1
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items:
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- const: core
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- enum:
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- coregroup
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- stacks
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- const: stacks
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nvmem-cells:
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items:
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- description: bitmask of functional shader cores
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nvmem-cell-names:
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items:
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- const: shader-present
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mali-supply: true
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operating-points-v2: true
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opp-table:
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type: object
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power-domains:
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minItems: 1
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maxItems: 5
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power-domain-names:
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minItems: 1
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maxItems: 5
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sram-supply: true
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"#cooling-cells":
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const: 2
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dynamic-power-coefficient:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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A u32 value that represents the running time dynamic
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power coefficient in units of uW/MHz/V^2. The
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coefficient can either be calculated from power
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measurements or derived by analysis.
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The dynamic power consumption of the GPU is
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proportional to the square of the Voltage (V) and
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the clock frequency (f). The coefficient is used to
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calculate the dynamic power as below -
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Pdyn = dynamic-power-coefficient * V^2 * f
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where voltage is in V, frequency is in MHz.
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dma-coherent: true
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-names
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- clocks
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additionalProperties: false
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: rockchip,rk3588-mali
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then:
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properties:
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clocks:
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minItems: 3
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nvmem-cells: false
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nvmem-cell-names: false
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power-domains:
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maxItems: 1
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power-domain-names: false
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required:
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- mali-supply
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- if:
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properties:
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compatible:
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contains:
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const: mediatek,mt8196-mali
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then:
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properties:
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mali-supply: false
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sram-supply: false
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operating-points-v2: false
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power-domains:
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maxItems: 1
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power-domain-names: false
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clocks:
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maxItems: 2
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clock-names:
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items:
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- const: core
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- const: stacks
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required:
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- nvmem-cells
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- nvmem-cell-names
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- power-domains
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examples:
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- |
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#include <dt-bindings/clock/rockchip,rk3588-cru.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/rk3588-power.h>
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gpu: gpu@fb000000 {
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compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
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reg = <0xfb000000 0x200000>;
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interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "job", "mmu", "gpu";
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clock-names = "core", "coregroup", "stacks";
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clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
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<&cru CLK_GPU_STACKS>;
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power-domains = <&power RK3588_PD_GPU>;
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operating-points-v2 = <&gpu_opp_table>;
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mali-supply = <&vdd_gpu_s0>;
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sram-supply = <&vdd_gpu_mem_s0>;
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gpu_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-300000000 {
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opp-hz = /bits/ 64 <300000000>;
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opp-microvolt = <675000 675000 850000>;
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};
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opp-400000000 {
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opp-hz = /bits/ 64 <400000000>;
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opp-microvolt = <675000 675000 850000>;
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};
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};
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};
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- |
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gpu@48000000 {
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compatible = "mediatek,mt8196-mali", "arm,mali-valhall-csf";
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reg = <0x48000000 0x480000>;
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clocks = <&gpufreq 0>, <&gpufreq 1>;
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clock-names = "core", "stacks";
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interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "job", "mmu", "gpu";
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nvmem-cells = <&shader_present>;
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nvmem-cell-names = "shader-present";
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power-domains = <&gpufreq>;
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};
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...
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