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ed8444006d
Mark the first 128 MiB of DRAM as reserved. The first 128 MiB of DRAM
may optionally be used by TFA and other firmware for its own purposes,
and in such case, Linux must not use this memory.
On this platform, U-Boot runs in EL3 and starts TFA BL31 and Linux from
a single combined fitImage. U-Boot has full access to all memory in the
0x40000000..0xbfffffff range, as well memory in the memory banks in the
64-bit address ranges, and therefore U-Boot patches this full complete
view of platform memory layout into the DT that is passed to the next
stage.
The next stage is TFA BL31 and then the Linux kernel. The TFA BL31 does
not modify the DT passed from U-Boot to TFA BL31 and then to Linux with
any new reserved-memory {} node to reserve memory areas used by the TFA
BL31 to prevent the next stage from using those areas, which lets Linux
to use all of the available DRAM as described in the DT that was passed
in by U-Boot, including the areas that are newly utilized by TFA BL31.
In case of high DRAM utilization, for example in case of four instances
of "memtester 3900M" running in parallel, unless the memory used by TFA
BL31 is properly reserved, Linux may use and corrupt the memory used by
TFA BL31, which would often lead to system becoming unresponsive.
Until TFA BL31 can properly fill its own reserved-memory node into the
DT, and to assure older versions of TFA BL31 do not cause problems, add
explicitly reserved-memory {} node which prevents Linux from using the
first 128 MiB of DRAM.
Note that TFA BL31 can be adjusted to use different memory areas, this
newly added reserved-memory {} node follows longer-term practice on the
R-Car SoCs where the first 128 MiB of DRAM is reserved for firmware use.
In case user does modify TFA BL31 to use different memory ranges, they
must either use a future version of TFA BL31 which properly patches a
reserved-memory {} node into the DT, or they must adjust the address
ranges of this reserved-memory {} node accordingly.
Fixes: a719915e76 ("arm64: dts: renesas: r8a779g3: Add Retronix R-Car V4H Sparrow Hawk board support")
Cc: stable@vger.kernel.org
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260324143342.17872-1-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
956 lines
18 KiB
Plaintext
956 lines
18 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the R-Car V4H ES3.0 Sparrow Hawk board
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*
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* Copyright (C) 2025 Marek Vasut <marek.vasut+renesas@mailbox.org>
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*/
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/*
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* DA7212 Codec settings
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*
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* for Playback
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* > amixer set "Headphone" 40%
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* > amixer set "Headphone" on
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* > amixer set "Mixout Left DAC Left" on
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* > amixer set "Mixout Right DAC Right" on
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* > aplay xxx.wav
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*
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* for Capture (Aux/Mic)
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*
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* on/off (B)
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* CONN3 (HeadSet) ---+----> MSIOF1
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* |
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* CONN4 AUX ---------+ on/off (A)
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*
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* > amixer set "Mixin PGA" on
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* > amixer set "Mixin PGA" 50%
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* > amixer set "ADC" on
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* > amixer set "ADC" 80%
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* > amixer set "Aux" on ^
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* > amixer set "Aux" 80% | (A)
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* > amixer set "Mixin Left Aux Left" on |
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* > amixer set "Mixin Right Aux Right" on v
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* > amixer set "Mic 1" on ^
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* > amixer set "Mic 1" 80% | (B)
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* > amixer set "Mixin Left Mic 1" on |
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* > amixer set "Mixin Right Mic 1" on v
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* > arecord -f cd xxx.wav
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/thermal/thermal.h>
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#include "r8a779g3.dtsi"
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/ {
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model = "Retronix Sparrow Hawk board based on r8a779g3";
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compatible = "retronix,sparrow-hawk", "renesas,r8a779g3",
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"renesas,r8a779g0";
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aliases {
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ethernet0 = &avb0;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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serial0 = &hscif0;
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serial1 = &hscif1;
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serial2 = &hscif3;
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spi0 = &rpc;
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};
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chosen {
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bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
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stdout-path = "serial0:921600n8";
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};
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/* Page 31 / FAN */
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fan: pwm-fan {
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pinctrl-0 = <&irq4_pins>;
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pinctrl-names = "default";
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compatible = "pwm-fan";
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#cooling-cells = <2>;
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interrupts-extended = <&intc_ex 4 IRQ_TYPE_EDGE_FALLING>;
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/*
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* The fan model connected to this device can be selected
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* by user. Set "cooling-levels" DT property to single 255
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* entry to force the fan PWM into constant HIGH, which
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* forces the fan to spin at maximum RPM, thus providing
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* maximum cooling to this device and protection against
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* misconfigured PWM duty cycle to the fan.
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*
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* User has to configure "pwms" and "pulses-per-revolution"
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* DT properties according to fan datasheet first, and then
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* extend "cooling-levels = <0 m n ... 255>" property to
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* achieve proper fan control compatible with fan model
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* installed by user.
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*/
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cooling-levels = <255>;
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pulses-per-revolution = <2>;
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pwms = <&pwm0 0 50000>;
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};
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/*
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* Page 15 / LPDDR5
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*
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* This configuration listed below is for the 8 GiB board variant
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* with MT62F1G64D8EK-023 WT:C LPDDR5 part populated on the board.
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*
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* A variant with 16 GiB MT62F2G64D8EK-023 WT:C part populated on
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* the board is automatically handled by the bootloader, which
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* adjusts the correct DRAM size into the memory nodes below.
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*/
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memory@48000000 {
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device_type = "memory";
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/* first 128MB is reserved for secure area. */
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reg = <0x0 0x48000000 0x0 0x78000000>;
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};
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memory@480000000 {
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device_type = "memory";
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reg = <0x4 0x80000000 0x0 0x80000000>;
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};
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memory@600000000 {
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device_type = "memory";
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reg = <0x6 0x00000000 0x1 0x00000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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tfa@40000000 {
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reg = <0x0 0x40000000 0x0 0x8000000>;
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no-map;
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};
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};
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/* Page 27 / DSI to Display */
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dp-con {
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compatible = "dp-connector";
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label = "CN6";
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type = "full-size";
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port {
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dp_con_in: endpoint {
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remote-endpoint = <&sn65dsi86_out>;
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};
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};
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};
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/* Page 26 / PCIe.0/1 CLK */
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pcie_refclk: clk-x8 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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reg_1p2v: regulator-1p2v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.2V";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_1p8v: regulator-1p8v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* Page 27 / DSI to Display */
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sn65dsi86_refclk: clk-x9 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <38400000>;
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};
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/* Page 30 / Audio_Codec */
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sound_card: sound {
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compatible = "audio-graph-card2";
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links = <&msiof1_snd>;
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};
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/* Page 17 uSD-Slot */
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vcc_sdhi: regulator-vcc-sdhi {
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compatible = "regulator-gpio";
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regulator-name = "SDHI VccQ";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&gpio8 13 GPIO_ACTIVE_HIGH>;
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gpios-states = <1>;
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states = <1800000 0>, <3300000 1>;
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};
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};
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/* Use thermal-idle cooling for all SoC cores */
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&a76_0 {
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#cooling-cells = <2>;
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a76_0_thermal_idle: thermal-idle {
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#cooling-cells = <2>;
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duration-us = <10000>;
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exit-latency-us = <500>;
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};
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};
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&a76_1 {
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a76_1_thermal_idle: thermal-idle {
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#cooling-cells = <2>;
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duration-us = <10000>;
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exit-latency-us = <500>;
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};
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};
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&a76_2 {
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a76_2_thermal_idle: thermal-idle {
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#cooling-cells = <2>;
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duration-us = <10000>;
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exit-latency-us = <500>;
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};
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};
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&a76_3 {
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a76_3_thermal_idle: thermal-idle {
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#cooling-cells = <2>;
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duration-us = <10000>;
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exit-latency-us = <500>;
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};
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};
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&audio_clkin {
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clock-frequency = <24576000>;
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};
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/* Page 22 / Ether_AVB0 */
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&avb0 {
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pinctrl-0 = <&avb0_pins>;
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pinctrl-names = "default";
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phy-handle = <&avb0_phy>;
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tx-internal-delay-ps = <2000>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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avb0_phy: ethernet-phy@0 { /* KSZ9031RNXVB */
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compatible = "ethernet-phy-id0022.1622",
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"ethernet-phy-ieee802.3-c22";
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rxc-skew-ps = <1500>;
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reg = <0>;
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/* AVB0_PHY_INT_V */
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interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>;
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/* GP7_10/AVB0_RESETN_V */
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reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10000>;
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reset-deassert-us = <300>;
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};
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};
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};
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/* Page 28 / CANFD_IF */
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&can_clk {
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clock-frequency = <40000000>;
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};
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/* Page 28 / CANFD_IF */
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&canfd {
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pinctrl-0 = <&canfd3_pins>, <&canfd4_pins>, <&can_clk_pins>;
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pinctrl-names = "default";
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status = "okay";
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channel3 {
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status = "okay";
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};
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channel4 {
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status = "okay";
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};
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};
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/* Page 27 / DSI to Display */
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&dsi1 {
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status = "okay";
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ports {
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port@1 {
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dsi1_out: endpoint {
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remote-endpoint = <&sn65dsi86_in>;
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data-lanes = <1 2 3 4>;
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};
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};
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};
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};
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/* Page 27 / DSI to Display */
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&du {
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status = "okay";
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};
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/* Page 5 / R-Car V4H_INT_I2C */
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&extal_clk { /* X3 */
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clock-frequency = <16666666>;
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};
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/* Page 5 / R-Car V4H_INT_I2C */
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&extalr_clk { /* X2 */
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clock-frequency = <32768>;
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};
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/* Page 26 / 2230 Key M M.2 */
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&gpio4 {
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/* 9FGV0441 nOE inputs 0 and 1 */
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pcie-m2-oe-hog {
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gpio-hog;
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gpios = <21 GPIO_ACTIVE_HIGH>;
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output-low;
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line-name = "PCIe-CLK-nOE-M2";
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};
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/* 9FGV0441 nOE inputs 2 and 3 */
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pcie-usb-oe-hog {
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gpio-hog;
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gpios = <22 GPIO_ACTIVE_HIGH>;
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output-low;
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line-name = "PCIe-CLK-nOE-USB";
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};
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};
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/* Page 23 / DEBUG */
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&hscif0 { /* FTDI ADBUS[3:0] */
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pinctrl-0 = <&hscif0_pins>;
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pinctrl-names = "default";
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uart-has-rtscts;
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bootph-all;
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status = "okay";
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};
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/* Page 23 / DEBUG */
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&hscif1 { /* FTDI BDBUS[3:0] */
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pinctrl-0 = <&hscif1_pins>;
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pinctrl-names = "default";
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uart-has-rtscts;
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status = "okay";
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};
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/* Page 24 / UART */
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&hscif3 { /* CN7 pins 8 (TX) and 10 (RX) */
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pinctrl-0 = <&hscif3_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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/* Page 24 / I2C SWITCH */
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&i2c0 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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clock-frequency = <400000>;
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status = "okay";
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mux@71 {
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compatible = "nxp,pca9544"; /* TCA9544 */
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reg = <0x71>;
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#address-cells = <1>;
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#size-cells = <0>;
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vdd-supply = <®_3p3v>;
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i2c0_mux0: i2c@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* Page 27 / DSI to Display */
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bridge@2c {
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pinctrl-0 = <&irq0_pins>;
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pinctrl-names = "default";
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compatible = "ti,sn65dsi86";
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reg = <0x2c>;
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clocks = <&sn65dsi86_refclk>;
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clock-names = "refclk";
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interrupts-extended = <&intc_ex 0 IRQ_TYPE_LEVEL_HIGH>;
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enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
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vccio-supply = <®_1p8v>;
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vpll-supply = <®_1p8v>;
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vcca-supply = <®_1p2v>;
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vcc-supply = <®_1p2v>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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sn65dsi86_in: endpoint {
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remote-endpoint = <&dsi1_out>;
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};
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};
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port@1 {
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reg = <1>;
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sn65dsi86_out: endpoint {
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remote-endpoint = <&dp_con_in>;
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};
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};
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};
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};
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};
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i2c0_mux1: i2c@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* Page 30 / Audio_Codec */
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codec@1a {
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compatible = "dlg,da7212";
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#sound-dai-cells = <0>;
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reg = <0x1a>;
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clocks = <&rcar_sound>;
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clock-names = "mclk";
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VDDA-supply = <®_1p8v>;
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VDDMIC-supply = <®_3p3v>;
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VDDIO-supply = <®_3p3v>;
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port {
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da7212_endpoint: endpoint {
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bitclock-master;
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frame-master;
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remote-endpoint = <&msiof1_snd_endpoint>;
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};
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};
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};
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};
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i2c0_mux2: i2c@2 {
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reg = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* Page 26 / PCIe.0/1 CLK */
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pcie_clk: clk@68 {
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compatible = "renesas,9fgv0441";
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reg = <0x68>;
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clocks = <&pcie_refclk>;
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#clock-cells = <1>;
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};
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};
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i2c0_mux3: i2c@3 {
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reg = <3>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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/* Page 29 / CSI_IF_CN / CAM_CN0 */
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&i2c1 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&i2c1_pins>;
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pinctrl-names = "default";
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};
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/* Page 29 / CSI_IF_CN / CAM_CN1 */
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&i2c2 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&i2c2_pins>;
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pinctrl-names = "default";
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};
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/* Page 31 / IO_CN */
|
|
&i2c3 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-0 = <&i2c3_pins>;
|
|
pinctrl-names = "default";
|
|
};
|
|
|
|
/* Page 31 / IO_CN */
|
|
&i2c4 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-0 = <&i2c4_pins>;
|
|
pinctrl-names = "default";
|
|
};
|
|
|
|
/* Page 18 / POWER_CORE and Page 19 / POWER_PMIC */
|
|
&i2c5 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-0 = <&i2c5_pins>;
|
|
pinctrl-names = "default";
|
|
};
|
|
|
|
/* Page 17 uSD-Slot */
|
|
&mmc0 {
|
|
pinctrl-0 = <&sd_pins>;
|
|
pinctrl-1 = <&sd_uhs_pins>;
|
|
pinctrl-names = "default", "state_uhs";
|
|
bus-width = <4>;
|
|
cd-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; /* SD_CD */
|
|
sd-uhs-sdr50;
|
|
sd-uhs-sdr104;
|
|
vmmc-supply = <®_3p3v>;
|
|
vqmmc-supply = <&vcc_sdhi>;
|
|
status = "okay";
|
|
};
|
|
|
|
&msiof1 {
|
|
pinctrl-0 = <&msiof1_pins>;
|
|
pinctrl-names = "default";
|
|
|
|
status = "okay";
|
|
|
|
/* ignore DT warning */
|
|
/delete-property/#address-cells;
|
|
/delete-property/#size-cells;
|
|
|
|
msiof1_snd: port {
|
|
msiof1_snd_endpoint: endpoint {
|
|
remote-endpoint = <&da7212_endpoint>;
|
|
};
|
|
};
|
|
};
|
|
|
|
/* Page 26 / 2230 Key M M.2 */
|
|
&pcie0_clkref {
|
|
status = "disabled";
|
|
};
|
|
|
|
&pciec0 {
|
|
clocks = <&cpg CPG_MOD 624>, <&pcie_clk 0>;
|
|
reset-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
|
|
status = "okay";
|
|
};
|
|
|
|
&pciec0_rp {
|
|
clocks = <&pcie_clk 1>;
|
|
vpcie3v3-supply = <®_3p3v>;
|
|
};
|
|
|
|
/* Page 25 / PCIe to USB */
|
|
&pcie1_clkref {
|
|
status = "disabled";
|
|
};
|
|
|
|
&pciec1 {
|
|
clocks = <&cpg CPG_MOD 625>, <&pcie_clk 2>;
|
|
/* uPD720201 is PCIe Gen2 x1 device */
|
|
num-lanes = <1>;
|
|
reset-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
|
|
status = "okay";
|
|
};
|
|
|
|
&pciec1_rp {
|
|
clocks = <&pcie_clk 3>;
|
|
vpcie3v3-supply = <®_3p3v>;
|
|
};
|
|
|
|
&pfc {
|
|
pinctrl-0 = <&scif_clk_pins>;
|
|
pinctrl-names = "default";
|
|
|
|
/* Page 22 / Ether_AVB0 */
|
|
avb0_pins: avb0 {
|
|
mux {
|
|
groups = "avb0_link", "avb0_mdio", "avb0_rgmii",
|
|
"avb0_txcrefclk";
|
|
function = "avb0";
|
|
};
|
|
|
|
pins-mdio {
|
|
groups = "avb0_mdio";
|
|
drive-strength = <21>;
|
|
};
|
|
|
|
pins-mii {
|
|
groups = "avb0_rgmii";
|
|
drive-strength = <21>;
|
|
};
|
|
|
|
pins-vddq18-25-avb {
|
|
pins = "PIN_VDDQ_AVB0", "PIN_VDDQ_AVB1", "PIN_VDDQ_AVB2", "PIN_VDDQ_TSN0";
|
|
power-source = <1800>;
|
|
};
|
|
};
|
|
|
|
/* Page 28 / CANFD_IF */
|
|
can_clk_pins: can-clk {
|
|
groups = "can_clk";
|
|
function = "can_clk";
|
|
};
|
|
|
|
/* Page 28 / CANFD_IF */
|
|
canfd3_pins: canfd3 {
|
|
groups = "canfd3_data";
|
|
function = "canfd3";
|
|
};
|
|
|
|
/* Page 28 / CANFD_IF */
|
|
canfd4_pins: canfd4 {
|
|
groups = "canfd4_data";
|
|
function = "canfd4";
|
|
};
|
|
|
|
/* Page 23 / DEBUG */
|
|
hscif0_pins: hscif0 {
|
|
groups = "hscif0_data", "hscif0_ctrl";
|
|
function = "hscif0";
|
|
};
|
|
|
|
/* Page 23 / DEBUG */
|
|
hscif1_pins: hscif1 {
|
|
groups = "hscif1_data_a", "hscif1_ctrl_a";
|
|
function = "hscif1";
|
|
};
|
|
|
|
/* Page 24 / UART */
|
|
hscif3_pins: hscif3 {
|
|
groups = "hscif3_data_a";
|
|
function = "hscif3";
|
|
};
|
|
|
|
/* Page 24 / I2C SWITCH */
|
|
i2c0_pins: i2c0 {
|
|
groups = "i2c0";
|
|
function = "i2c0";
|
|
};
|
|
|
|
/* Page 29 / CSI_IF_CN / CAM_CN0 */
|
|
i2c1_pins: i2c1 {
|
|
groups = "i2c1";
|
|
function = "i2c1";
|
|
};
|
|
|
|
/* Page 29 / CSI_IF_CN / CAM_CN1 */
|
|
i2c2_pins: i2c2 {
|
|
groups = "i2c2";
|
|
function = "i2c2";
|
|
};
|
|
|
|
/* Page 31 / IO_CN */
|
|
i2c3_pins: i2c3 {
|
|
groups = "i2c3";
|
|
function = "i2c3";
|
|
};
|
|
|
|
/* Page 31 / IO_CN */
|
|
i2c4_pins: i2c4 {
|
|
groups = "i2c4";
|
|
function = "i2c4";
|
|
};
|
|
|
|
/* Page 18 / POWER_CORE */
|
|
i2c5_pins: i2c5 {
|
|
groups = "i2c5";
|
|
function = "i2c5";
|
|
};
|
|
|
|
/* Page 27 / DSI to Display */
|
|
irq0_pins: irq0 {
|
|
groups = "intc_ex_irq0_a";
|
|
function = "intc_ex";
|
|
};
|
|
|
|
/* Page 31 / FAN */
|
|
irq4_pins: irq4 {
|
|
groups = "intc_ex_irq4_b";
|
|
function = "intc_ex";
|
|
};
|
|
|
|
/* Page 31 / FAN */
|
|
pwm0_pins: pwm0 {
|
|
groups = "pwm0";
|
|
function = "pwm0";
|
|
};
|
|
|
|
/* Page 31 / CN7 pin 12 */
|
|
pwm1_pins: pwm1 {
|
|
groups = "pwm1_b";
|
|
function = "pwm1";
|
|
};
|
|
|
|
/* Page 31 / CN7 pin 32 */
|
|
pwm6_pins: pwm6 {
|
|
groups = "pwm6";
|
|
function = "pwm6";
|
|
};
|
|
|
|
/* Page 31 / CN7 pin 33 */
|
|
pwm7_pins: pwm7 {
|
|
groups = "pwm7";
|
|
function = "pwm7";
|
|
};
|
|
|
|
/* Page 16 / QSPI_FLASH */
|
|
qspi0_pins: qspi0 {
|
|
groups = "qspi0_ctrl", "qspi0_data4";
|
|
function = "qspi0";
|
|
bootph-all;
|
|
};
|
|
|
|
/* Page 6 / SCIF_CLK_SOC_V */
|
|
scif_clk_pins: scif-clk {
|
|
groups = "scif_clk";
|
|
function = "scif_clk";
|
|
};
|
|
|
|
/* Page 17 uSD-Slot */
|
|
sd_pins: sd {
|
|
groups = "mmc_data4", "mmc_ctrl";
|
|
function = "mmc";
|
|
power-source = <3300>;
|
|
};
|
|
|
|
/* Page 17 uSD-Slot */
|
|
sd_uhs_pins: sd-uhs {
|
|
groups = "mmc_data4", "mmc_ctrl";
|
|
function = "mmc";
|
|
power-source = <1800>;
|
|
};
|
|
|
|
/* Page 30 / Audio_Codec */
|
|
msiof1_pins: sound {
|
|
groups = "msiof1_clk", "msiof1_sync", "msiof1_txd", "msiof1_rxd";
|
|
function = "msiof1";
|
|
};
|
|
|
|
/* Page 30 / Audio_Codec */
|
|
sound_clk_pins: sound-clk {
|
|
groups = "audio_clkin", "audio_clkout";
|
|
function = "audio_clk";
|
|
};
|
|
};
|
|
|
|
/* Page 31 / FAN */
|
|
&pwm0 {
|
|
pinctrl-0 = <&pwm0_pins>;
|
|
pinctrl-names = "default";
|
|
status = "okay";
|
|
};
|
|
|
|
/* Page 31 / CN7 pin 12 */
|
|
&pwm1 {
|
|
pinctrl-0 = <&pwm1_pins>;
|
|
pinctrl-names = "default";
|
|
status = "okay";
|
|
};
|
|
|
|
/* Page 31 / CN7 pin 32 */
|
|
&pwm6 {
|
|
pinctrl-0 = <&pwm6_pins>;
|
|
pinctrl-names = "default";
|
|
status = "okay";
|
|
};
|
|
|
|
/* Page 31 / CN7 pin 33 */
|
|
&pwm7 {
|
|
pinctrl-0 = <&pwm7_pins>;
|
|
pinctrl-names = "default";
|
|
status = "okay";
|
|
};
|
|
|
|
/* Page 30 / Audio_Codec */
|
|
&rcar_sound {
|
|
pinctrl-0 = <&sound_clk_pins>;
|
|
pinctrl-names = "default";
|
|
|
|
/* It is used for ADG output as DA7212_MCLK */
|
|
|
|
/* audio_clkout */
|
|
clock-frequency = <12288000>; /* 48 kHz groups */
|
|
|
|
status = "okay";
|
|
};
|
|
|
|
/* Page 16 / QSPI_FLASH */
|
|
&rpc {
|
|
pinctrl-0 = <&qspi0_pins>;
|
|
pinctrl-names = "default";
|
|
bootph-all;
|
|
|
|
status = "okay";
|
|
|
|
flash@0 {
|
|
/*
|
|
* EVTA1 is populated with Spansion S25FS512S
|
|
* EVTB1 is populated with Winbond W77Q51NW
|
|
*/
|
|
compatible = "jedec,spi-nor";
|
|
reg = <0>;
|
|
spi-max-frequency = <40000000>;
|
|
spi-rx-bus-width = <4>;
|
|
spi-tx-bus-width = <4>;
|
|
bootph-all;
|
|
|
|
partitions {
|
|
compatible = "fixed-partitions";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
boot@0 {
|
|
reg = <0x0 0x1000000>;
|
|
read-only;
|
|
};
|
|
|
|
user@1000000 {
|
|
reg = <0x1000000 0x2f80000>;
|
|
};
|
|
|
|
env1@3f80000 {
|
|
reg = <0x3f80000 0x40000>;
|
|
};
|
|
|
|
env2@3fc0000 {
|
|
reg = <0x3fc0000 0x40000>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&rwdt {
|
|
timeout-sec = <60>;
|
|
status = "okay";
|
|
};
|
|
|
|
/* Page 6 / SCIF_CLK_SOC_V */
|
|
&scif_clk { /* X12 */
|
|
clock-frequency = <24000000>;
|
|
};
|
|
|
|
/* THS sensors in SoC, critical temperature trip point is 100C */
|
|
&sensor1_crit {
|
|
temperature = <100000>;
|
|
};
|
|
|
|
&sensor2_crit {
|
|
temperature = <100000>;
|
|
};
|
|
|
|
&sensor3_crit {
|
|
temperature = <100000>;
|
|
};
|
|
|
|
&sensor4_crit {
|
|
temperature = <100000>;
|
|
};
|
|
|
|
/* THS sensor in SoC near CA76 cores does more progressive cooling. */
|
|
&sensor_thermal_ca76 {
|
|
critical-action = "shutdown";
|
|
|
|
cooling-maps {
|
|
/*
|
|
* The cooling-device minimum and maximum parameters inversely
|
|
* match opp-table-0 {} node entries in r8a779g0.dtsi, in other
|
|
* words, 0 refers to 1.8 GHz OPP and 4 refers to 500 MHz OPP.
|
|
* This is because they refer to cooling levels, where maximum
|
|
* cooling level happens at 500 MHz OPP, when the CPU core is
|
|
* running slowly and therefore generates least heat.
|
|
*/
|
|
map0 {
|
|
/* At 68C, inhibit 1.7 GHz and 1.8 GHz modes */
|
|
trip = <&sensor3_passive_low>;
|
|
cooling-device = <&a76_0 2 4>;
|
|
contribution = <128>;
|
|
};
|
|
|
|
map1 {
|
|
/* At 72C, inhibit 1.5 GHz mode */
|
|
trip = <&sensor3_passive_mid>;
|
|
cooling-device = <&a76_0 3 4>;
|
|
contribution = <256>;
|
|
};
|
|
|
|
map2 {
|
|
/* At 76C, start injecting idle states 0..80% of time */
|
|
trip = <&sensor3_passive_hi>;
|
|
cooling-device = <&a76_0_thermal_idle 0 80>,
|
|
<&a76_1_thermal_idle 0 80>,
|
|
<&a76_2_thermal_idle 0 80>,
|
|
<&a76_3_thermal_idle 0 80>;
|
|
contribution = <512>;
|
|
};
|
|
|
|
map3 {
|
|
/* At 80C, inhibit 1.0 GHz mode */
|
|
trip = <&sensor3_passive_crit>;
|
|
cooling-device = <&a76_0 4 4>;
|
|
contribution = <1024>;
|
|
};
|
|
};
|
|
|
|
trips {
|
|
sensor3_passive_low: sensor3-passive-low {
|
|
temperature = <68000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
sensor3_passive_mid: sensor3-passive-mid {
|
|
temperature = <72000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
sensor3_passive_hi: sensor3-passive-hi {
|
|
temperature = <76000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
sensor3_passive_crit: sensor3-passive-crit {
|
|
temperature = <80000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
&sensor_thermal_cnn {
|
|
critical-action = "shutdown";
|
|
};
|
|
|
|
&sensor_thermal_cr52 {
|
|
critical-action = "shutdown";
|
|
};
|
|
|
|
&sensor_thermal_ddr1 {
|
|
critical-action = "shutdown";
|
|
};
|