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c19f5a0341
Hook up the display fault irq handlers for VLV/CHV.
Unfortunately the actual hardware doesn't agree with the
spec on how DPINVGTT should behave. The docs claim that
the status bits can be cleared by writing '1' to them,
but in reality there doesn't seem to be any way to clear
them. So we must disable and ignore any fault we've already
seen in the past. The entire register does reset when
the display power well goes down, so we can just always
re-enable all the bits in irq postinstall without having
to track the state beyond that.
v2: Use intel_display instead of dev_priv
Move xe gen2_error_{init,reset}() out
Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250217070047.953-9-ville.syrjala@linux.intel.com
87 lines
3.8 KiB
C
87 lines
3.8 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef __INTEL_DISPLAY_IRQ_H__
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#define __INTEL_DISPLAY_IRQ_H__
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#include <linux/types.h>
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#include "intel_display_limits.h"
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enum pipe;
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struct drm_crtc;
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struct drm_i915_private;
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struct intel_display;
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void valleyview_enable_display_irqs(struct drm_i915_private *i915);
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void valleyview_disable_display_irqs(struct drm_i915_private *i915);
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void ilk_update_display_irq(struct drm_i915_private *i915,
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u32 interrupt_mask, u32 enabled_irq_mask);
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void ilk_enable_display_irq(struct drm_i915_private *i915, u32 bits);
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void ilk_disable_display_irq(struct drm_i915_private *i915, u32 bits);
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void bdw_update_port_irq(struct drm_i915_private *i915, u32 interrupt_mask, u32 enabled_irq_mask);
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void bdw_enable_pipe_irq(struct drm_i915_private *i915, enum pipe pipe, u32 bits);
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void bdw_disable_pipe_irq(struct drm_i915_private *i915, enum pipe pipe, u32 bits);
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void ibx_display_interrupt_update(struct drm_i915_private *i915,
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u32 interrupt_mask, u32 enabled_irq_mask);
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void ibx_enable_display_interrupt(struct drm_i915_private *i915, u32 bits);
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void ibx_disable_display_interrupt(struct drm_i915_private *i915, u32 bits);
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void gen8_irq_power_well_post_enable(struct drm_i915_private *i915, u8 pipe_mask);
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void gen8_irq_power_well_pre_disable(struct drm_i915_private *i915, u8 pipe_mask);
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int i8xx_enable_vblank(struct drm_crtc *crtc);
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int i915gm_enable_vblank(struct drm_crtc *crtc);
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int i965_enable_vblank(struct drm_crtc *crtc);
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int ilk_enable_vblank(struct drm_crtc *crtc);
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int bdw_enable_vblank(struct drm_crtc *crtc);
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void i8xx_disable_vblank(struct drm_crtc *crtc);
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void i915gm_disable_vblank(struct drm_crtc *crtc);
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void i965_disable_vblank(struct drm_crtc *crtc);
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void ilk_disable_vblank(struct drm_crtc *crtc);
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void bdw_disable_vblank(struct drm_crtc *crtc);
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void ivb_display_irq_handler(struct drm_i915_private *i915, u32 de_iir);
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void ilk_display_irq_handler(struct drm_i915_private *i915, u32 de_iir);
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void gen8_de_irq_handler(struct drm_i915_private *i915, u32 master_ctl);
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void gen11_display_irq_handler(struct drm_i915_private *i915);
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u32 gen11_gu_misc_irq_ack(struct drm_i915_private *i915, const u32 master_ctl);
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void gen11_gu_misc_irq_handler(struct drm_i915_private *i915, const u32 iir);
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void i9xx_display_irq_reset(struct drm_i915_private *i915);
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void vlv_display_irq_reset(struct drm_i915_private *i915);
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void gen8_display_irq_reset(struct drm_i915_private *i915);
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void gen11_display_irq_reset(struct drm_i915_private *i915);
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void vlv_display_irq_postinstall(struct drm_i915_private *i915);
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void ilk_de_irq_postinstall(struct drm_i915_private *i915);
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void gen8_de_irq_postinstall(struct drm_i915_private *i915);
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void gen11_de_irq_postinstall(struct drm_i915_private *i915);
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void dg1_de_irq_postinstall(struct drm_i915_private *i915);
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u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe);
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void i915_enable_pipestat(struct drm_i915_private *i915, enum pipe pipe, u32 status_mask);
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void i915_disable_pipestat(struct drm_i915_private *i915, enum pipe pipe, u32 status_mask);
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void i915_enable_asle_pipestat(struct drm_i915_private *i915);
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void i9xx_pipestat_irq_ack(struct drm_i915_private *i915, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
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void i915_pipestat_irq_handler(struct drm_i915_private *i915, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
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void i965_pipestat_irq_handler(struct drm_i915_private *i915, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
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void valleyview_pipestat_irq_handler(struct drm_i915_private *i915, u32 pipe_stats[I915_MAX_PIPES]);
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void vlv_display_error_irq_ack(struct intel_display *display, u32 *eir, u32 *dpinvgtt);
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void vlv_display_error_irq_handler(struct intel_display *display, u32 eir, u32 dpinvgtt);
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void intel_display_irq_init(struct drm_i915_private *i915);
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void i915gm_irq_cstate_wa(struct drm_i915_private *i915, bool enable);
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#endif /* __INTEL_DISPLAY_IRQ_H__ */
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