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765425f598
In order to reduce the DC5->DC2 restore time, wakelocks have been introduced in DMC so the driver can tell it when registers and other memory areas are going to be accessed and keep their respective blocks awake. Implement this in the driver by adding the concept of DMC wakelocks. When the driver needs to access memory which lies inside pre-defined ranges, it will tell DMC to set the wakelock, access the memory, then wait for a while and clear the wakelock. The wakelock state is protected in the driver with spinlocks to prevent concurrency issues. BSpec: 71583 Signed-off-by: Luca Coelho <luciano.coelho@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240412094148.808179-2-luciano.coelho@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
208 lines
4.5 KiB
C
208 lines
4.5 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_DE_H__
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#define __INTEL_DE_H__
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include "intel_uncore.h"
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static inline u32
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intel_de_read(struct drm_i915_private *i915, i915_reg_t reg)
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{
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u32 val;
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intel_dmc_wl_get(i915, reg);
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val = intel_uncore_read(&i915->uncore, reg);
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intel_dmc_wl_put(i915, reg);
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return val;
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}
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static inline u8
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intel_de_read8(struct drm_i915_private *i915, i915_reg_t reg)
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{
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u8 val;
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intel_dmc_wl_get(i915, reg);
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val = intel_uncore_read8(&i915->uncore, reg);
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intel_dmc_wl_put(i915, reg);
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return val;
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}
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static inline u64
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intel_de_read64_2x32(struct drm_i915_private *i915,
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i915_reg_t lower_reg, i915_reg_t upper_reg)
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{
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u64 val;
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intel_dmc_wl_get(i915, lower_reg);
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intel_dmc_wl_get(i915, upper_reg);
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val = intel_uncore_read64_2x32(&i915->uncore, lower_reg, upper_reg);
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intel_dmc_wl_put(i915, upper_reg);
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intel_dmc_wl_put(i915, lower_reg);
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return val;
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}
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static inline void
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intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg)
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{
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intel_dmc_wl_get(i915, reg);
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intel_uncore_posting_read(&i915->uncore, reg);
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intel_dmc_wl_put(i915, reg);
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}
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static inline void
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intel_de_write(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
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{
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intel_dmc_wl_get(i915, reg);
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intel_uncore_write(&i915->uncore, reg, val);
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intel_dmc_wl_put(i915, reg);
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}
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static inline u32
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__intel_de_rmw_nowl(struct drm_i915_private *i915, i915_reg_t reg,
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u32 clear, u32 set)
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{
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return intel_uncore_rmw(&i915->uncore, reg, clear, set);
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}
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static inline u32
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intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set)
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{
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u32 val;
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intel_dmc_wl_get(i915, reg);
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val = __intel_de_rmw_nowl(i915, reg, clear, set);
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intel_dmc_wl_put(i915, reg);
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return val;
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}
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static inline int
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__intel_wait_for_register_nowl(struct drm_i915_private *i915, i915_reg_t reg,
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u32 mask, u32 value, unsigned int timeout)
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{
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return intel_wait_for_register(&i915->uncore, reg, mask,
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value, timeout);
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}
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static inline int
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intel_de_wait(struct drm_i915_private *i915, i915_reg_t reg,
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u32 mask, u32 value, unsigned int timeout)
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{
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int ret;
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intel_dmc_wl_get(i915, reg);
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ret = __intel_wait_for_register_nowl(i915, reg, mask, value, timeout);
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intel_dmc_wl_put(i915, reg);
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return ret;
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}
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static inline int
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intel_de_wait_fw(struct drm_i915_private *i915, i915_reg_t reg,
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u32 mask, u32 value, unsigned int timeout)
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{
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int ret;
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intel_dmc_wl_get(i915, reg);
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ret = intel_wait_for_register_fw(&i915->uncore, reg, mask, value, timeout);
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intel_dmc_wl_put(i915, reg);
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return ret;
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}
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static inline int
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intel_de_wait_custom(struct drm_i915_private *i915, i915_reg_t reg,
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u32 mask, u32 value,
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unsigned int fast_timeout_us,
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unsigned int slow_timeout_ms, u32 *out_value)
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{
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int ret;
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intel_dmc_wl_get(i915, reg);
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ret = __intel_wait_for_register(&i915->uncore, reg, mask, value,
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fast_timeout_us, slow_timeout_ms, out_value);
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intel_dmc_wl_put(i915, reg);
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return ret;
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}
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static inline int
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intel_de_wait_for_set(struct drm_i915_private *i915, i915_reg_t reg,
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u32 mask, unsigned int timeout)
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{
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return intel_de_wait(i915, reg, mask, mask, timeout);
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}
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static inline int
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intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t reg,
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u32 mask, unsigned int timeout)
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{
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return intel_de_wait(i915, reg, mask, 0, timeout);
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}
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/*
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* Unlocked mmio-accessors, think carefully before using these.
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*
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* Certain architectures will die if the same cacheline is concurrently accessed
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* by different clients (e.g. on Ivybridge). Access to registers should
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* therefore generally be serialised, by either the dev_priv->uncore.lock or
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* a more localised lock guarding all access to that bank of registers.
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*/
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static inline u32
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intel_de_read_fw(struct drm_i915_private *i915, i915_reg_t reg)
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{
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u32 val;
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val = intel_uncore_read_fw(&i915->uncore, reg);
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trace_i915_reg_rw(false, reg, val, sizeof(val), true);
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return val;
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}
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static inline void
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intel_de_write_fw(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
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{
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trace_i915_reg_rw(true, reg, val, sizeof(val), true);
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intel_uncore_write_fw(&i915->uncore, reg, val);
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}
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static inline u32
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intel_de_read_notrace(struct drm_i915_private *i915, i915_reg_t reg)
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{
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return intel_uncore_read_notrace(&i915->uncore, reg);
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}
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static inline void
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intel_de_write_notrace(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
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{
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intel_uncore_write_notrace(&i915->uncore, reg, val);
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}
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#endif /* __INTEL_DE_H__ */
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