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MPAM (Memory Partitioning and Monitoring) is now exposed to user-space via resctrl. Add some documentation so the user knows what features to expect. Reviewed-by: Zeng Heng <zengheng4@huawei.com> Reviewed-by: Shaopeng Tan <tan.shaopeng@jp.fujitsu.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Ben Horgan <ben.horgan@arm.com> Reviewed-by: Gavin Shan <gshan@redhat.com> Tested-by: Gavin Shan <gshan@redhat.com> Tested-by: Shaopeng Tan <tan.shaopeng@jp.fujitsu.com> Tested-by: Jesse Chick <jessechick@os.amperecomputing.com> Signed-off-by: James Morse <james.morse@arm.com>
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3.2 KiB
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73 lines
3.2 KiB
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.. SPDX-License-Identifier: GPL-2.0
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====
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MPAM
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====
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What is MPAM
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============
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MPAM (Memory Partitioning and Monitoring) is a feature in the CPUs and memory
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system components such as the caches or memory controllers that allow memory
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traffic to be labelled, partitioned and monitored.
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Traffic is labelled by the CPU, based on the control or monitor group the
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current task is assigned to using resctrl. Partitioning policy can be set
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using the schemata file in resctrl, and monitor values read via resctrl.
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See Documentation/filesystems/resctrl.rst for more details.
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This allows tasks that share memory system resources, such as caches, to be
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isolated from each other according to the partitioning policy (so called noisy
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neighbours).
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Supported Platforms
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===================
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Use of this feature requires CPU support, support in the memory system
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components, and a description from firmware of where the MPAM device controls
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are in the MMIO address space. (e.g. the 'MPAM' ACPI table).
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The MMIO device that provides MPAM controls/monitors for a memory system
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component is called a memory system component. (MSC).
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Because the user interface to MPAM is via resctrl, only MPAM features that are
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compatible with resctrl can be exposed to user-space.
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MSC are considered as a group based on the topology. MSC that correspond with
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the L3 cache are considered together, it is not possible to mix MSC between L2
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and L3 to 'cover' a resctrl schema.
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The supported features are:
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* Cache portion bitmap controls (CPOR) on the L2 or L3 caches. To expose
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CPOR at L2 or L3, every CPU must have a corresponding CPU cache at this
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level that also supports the feature. Mismatched big/little platforms are
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not supported as resctrl's controls would then also depend on task
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placement.
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* Memory bandwidth maximum controls (MBW_MAX) on or after the L3 cache.
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resctrl uses the L3 cache-id to identify where the memory bandwidth
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control is applied. For this reason the platform must have an L3 cache
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with cache-id's supplied by firmware. (It doesn't need to support MPAM.)
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To be exported as the 'MB' schema, the topology of the group of MSC chosen
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must match the topology of the L3 cache so that the cache-id's can be
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repainted. For example: Platforms with Memory bandwidth maximum controls
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on CPU-less NUMA nodes cannot expose the 'MB' schema to resctrl as these
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nodes do not have a corresponding L3 cache. If the memory bandwidth
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control is on the memory rather than the L3 then there must be a single
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global L3 as otherwise it is unknown which L3 the traffic came from. There
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must be no caches between the L3 and the memory so that the two ends of
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the path have equivalent traffic.
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When the MPAM driver finds multiple groups of MSC it can use for the 'MB'
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schema, it prefers the group closest to the L3 cache.
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* Cache Storage Usage (CSU) counters can expose the 'llc_occupancy' provided
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there is at least one CSU monitor on each MSC that makes up the L3 group.
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Exposing CSU counters from other caches or devices is not supported.
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Reporting Bugs
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==============
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If you are not seeing the counters or controls you expect please share the
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debug messages produced when enabling dynamic debug and booting with:
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dyndbg="file mpam_resctrl.c +pl"
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