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b74d1315ca
Add a Intel event file for perf.
Committer note:
Testing it on a ThinkPad t450s:
[acme@jouet linux]$ perf list
<SNIP>
Cache:
l1d.replacement
[L1D data line replacements]
l1d_pend_miss.fb_full
[Cycles a demand request was blocked due to Fill Buffers inavailability]
l1d_pend_miss.pending
[L1D miss oustandings duration in cycles]
l1d_pend_miss.pending_cycles
[Cycles with L1D load Misses outstanding]
<SNIP>
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Tested-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Link: http://lkml.kernel.org/n/tip-3qh7e0quf7qlttjoz250hfcl@git.kernel.org
[ Lowercased the directory and file names ]
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
44 lines
2.0 KiB
JSON
44 lines
2.0 KiB
JSON
[
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{
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"PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.",
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"EventCode": "0x5C",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EventName": "CPL_CYCLES.RING0",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Unhalted core cycles when the thread is in ring 0",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.",
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"EventCode": "0x5C",
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"Counter": "0,1,2,3",
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"UMask": "0x2",
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"EventName": "CPL_CYCLES.RING123",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.",
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"EventCode": "0x5C",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EdgeDetect": "1",
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"EventName": "CPL_CYCLES.RING0_TRANS",
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"SampleAfterValue": "100007",
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"BriefDescription": "Number of intervals between processor halts while thread is in ring 0",
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"CounterMask": "1",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.",
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"EventCode": "0x63",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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}
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] |