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dcfbad10c7
Add a Intel event file for perf. Signed-off-by: Andi Kleen <ak@linux.intel.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Link: http://lkml.kernel.org/n/tip-q87xlo75ffonydbmvf6lr18n@git.kernel.org [ Lowercased the directory and file names ] Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
43 lines
1.6 KiB
JSON
43 lines
1.6 KiB
JSON
[
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{
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"PublicDescription": "Unhalted core cycles when the thread is in ring 0.",
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"EventCode": "0x5C",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EventName": "CPL_CYCLES.RING0",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Unhalted core cycles when the thread is in ring 0",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",
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"EventCode": "0x5C",
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"Counter": "0,1,2,3",
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"UMask": "0x2",
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"EventName": "CPL_CYCLES.RING123",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x5C",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EdgeDetect": "1",
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"EventName": "CPL_CYCLES.RING0_TRANS",
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"SampleAfterValue": "100003",
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"BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
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"CounterMask": "1",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.",
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"EventCode": "0x63",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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}
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] |