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55d42d272e
Add a Intel event file for perf. Signed-off-by: Andi Kleen <ak@linux.intel.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Link: http://lkml.kernel.org/n/tip-3x2we5evro8uhwmergz1mbd7@git.kernel.org [ Lowercased the directory and file names ] Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
34 lines
1.1 KiB
JSON
34 lines
1.1 KiB
JSON
[
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{
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"EventCode": "0x80",
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"Counter": "0,1",
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"UMask": "0x3",
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"EventName": "ICACHE.ACCESSES",
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"SampleAfterValue": "200003",
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"BriefDescription": "Counts all instruction fetches, including uncacheable fetches."
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},
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{
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"EventCode": "0x80",
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"Counter": "0,1",
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"UMask": "0x1",
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"EventName": "ICACHE.HIT",
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"SampleAfterValue": "200003",
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"BriefDescription": "Counts all instruction fetches that hit the instruction cache."
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},
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{
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"EventCode": "0x80",
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"Counter": "0,1",
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"UMask": "0x2",
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"EventName": "ICACHE.MISSES",
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"SampleAfterValue": "200003",
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"BriefDescription": "Counts all instruction fetches that miss the instruction cache or produce memory requests. An instruction fetch miss is counted only once and not once for every cycle it is outstanding."
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},
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{
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"EventCode": "0xE7",
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"Counter": "0,1",
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"UMask": "0x1",
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"EventName": "MS_DECODED.MS_ENTRY",
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"SampleAfterValue": "200003",
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"BriefDescription": "Counts the number of times the MSROM starts a flow of uops."
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}
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] |