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1b09784583
Add a Intel event file for perf. Signed-off-by: Andi Kleen <ak@linux.intel.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Link: http://lkml.kernel.org/n/tip-m72axmpkxcdproq9x04zulqs@git.kernel.org [ Lowercased the directory and file names ] Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
69 lines
3.2 KiB
JSON
69 lines
3.2 KiB
JSON
[
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{
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"PEBS": "1",
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"PublicDescription": "This event counts the number of load ops retired that had DTLB miss.",
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"EventCode": "0x04",
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"Counter": "0,1",
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"UMask": "0x8",
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"EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS",
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"SampleAfterValue": "200003",
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"BriefDescription": "Loads missed DTLB"
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},
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{
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"PublicDescription": "This event counts when a data (D) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.",
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"EventCode": "0x05",
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"Counter": "0,1",
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"UMask": "0x1",
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"EventName": "PAGE_WALKS.D_SIDE_WALKS",
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"SampleAfterValue": "100003",
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"BriefDescription": "D-side page-walks",
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"EdgeDetect": "1"
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},
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{
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"PublicDescription": "This event counts every cycle when a D-side (walks due to a load) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.",
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"EventCode": "0x05",
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"Counter": "0,1",
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"UMask": "0x1",
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"EventName": "PAGE_WALKS.D_SIDE_CYCLES",
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"SampleAfterValue": "200003",
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"BriefDescription": "Duration of D-side page-walks in core cycles"
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},
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{
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"PublicDescription": "This event counts when an instruction (I) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.",
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"EventCode": "0x05",
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"Counter": "0,1",
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"UMask": "0x2",
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"EventName": "PAGE_WALKS.I_SIDE_WALKS",
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"SampleAfterValue": "100003",
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"BriefDescription": "I-side page-walks",
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"EdgeDetect": "1"
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},
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{
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"PublicDescription": "This event counts every cycle when a I-side (walks due to an instruction fetch) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.",
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"EventCode": "0x05",
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"Counter": "0,1",
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"UMask": "0x2",
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"EventName": "PAGE_WALKS.I_SIDE_CYCLES",
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"SampleAfterValue": "200003",
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"BriefDescription": "Duration of I-side page-walks in core cycles"
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},
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{
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"PublicDescription": "This event counts when a data (D) page walk or an instruction (I) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.",
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"EventCode": "0x05",
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"Counter": "0,1",
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"UMask": "0x3",
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"EventName": "PAGE_WALKS.WALKS",
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"SampleAfterValue": "100003",
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"BriefDescription": "Total page walks that are completed (I-side and D-side)",
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"EdgeDetect": "1"
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},
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{
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"PublicDescription": "This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress. Since a pagewalk implies a TLB miss, the approximate cost of a TLB miss can be determined from this event.",
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"EventCode": "0x05",
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"Counter": "0,1",
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"UMask": "0x3",
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"EventName": "PAGE_WALKS.CYCLES",
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"SampleAfterValue": "200003",
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"BriefDescription": "Total cycles for all the page walks. (I-side and D-side)"
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}
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] |