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60772c225f
Add DPU version 13.0 for Qualcomm Kaanapali Soc. The Kaanapali DPU and SM8750 have significant differences, including additions and removals of registers, as well as changes in register addresses. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/698694/ Link: https://lore.kernel.org/r/20260115092749.533-2-yuanjie.yang@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
139 lines
3.3 KiB
YAML
139 lines
3.3 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/qcom,sm8650-dpu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SM8650 Display DPU
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maintainers:
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- Neil Armstrong <neil.armstrong@linaro.org>
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$ref: /schemas/display/msm/dpu-common.yaml#
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properties:
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compatible:
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oneOf:
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- enum:
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- qcom,glymur-dpu
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- qcom,kaanapali-dpu
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- qcom,sa8775p-dpu
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- qcom,sm8650-dpu
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- qcom,sm8750-dpu
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- qcom,x1e80100-dpu
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- items:
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- enum:
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- qcom,qcs8300-dpu
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- const: qcom,sa8775p-dpu
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reg:
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items:
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- description: Address offset and size for mdp register set
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- description: Address offset and size for vbif register set
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reg-names:
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items:
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- const: mdp
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- const: vbif
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clocks:
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items:
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- description: Display hf axi
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- description: Display MDSS ahb
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- description: Display lut
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- description: Display core
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- description: Display vsync
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clock-names:
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items:
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- const: nrt_bus
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- const: iface
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- const: lut
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- const: core
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- const: vsync
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/qcom,rpmhpd.h>
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display-controller@ae01000 {
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compatible = "qcom,sm8650-dpu";
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reg = <0x0ae01000 0x8f000>,
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<0x0aeb0000 0x2008>;
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reg-names = "mdp", "vbif";
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clocks = <&gcc_axi_clk>,
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<&dispcc_ahb_clk>,
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<&dispcc_mdp_lut_clk>,
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<&dispcc_mdp_clk>,
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<&dispcc_vsync_clk>;
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clock-names = "nrt_bus",
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"iface",
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"lut",
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"core",
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"vsync";
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assigned-clocks = <&dispcc_vsync_clk>;
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assigned-clock-rates = <19200000>;
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operating-points-v2 = <&mdp_opp_table>;
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power-domains = <&rpmhpd RPMHPD_MMCX>;
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interrupt-parent = <&mdss>;
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interrupts = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dpu_intf1_out: endpoint {
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remote-endpoint = <&dsi0_in>;
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};
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};
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port@1 {
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reg = <1>;
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dpu_intf2_out: endpoint {
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remote-endpoint = <&dsi1_in>;
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};
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};
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};
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mdp_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-200000000 {
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opp-hz = /bits/ 64 <200000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-325000000 {
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opp-hz = /bits/ 64 <325000000>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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opp-375000000 {
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opp-hz = /bits/ 64 <375000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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opp-514000000 {
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opp-hz = /bits/ 64 <514000000>;
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required-opps = <&rpmhpd_opp_nom>;
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};
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};
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};
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...
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