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Add device tree bindings for global clock controller on Glymur SoC. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250825-glymur-clock-controller-v5-v5-6-01b8c8681bcd@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
579 lines
22 KiB
C
579 lines
22 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GCC_GLYMUR_H
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#define _DT_BINDINGS_CLK_QCOM_GCC_GLYMUR_H
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/* GCC clocks */
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#define GCC_GPLL0 0
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#define GCC_GPLL0_OUT_EVEN 1
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#define GCC_GPLL1 2
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#define GCC_GPLL14 3
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#define GCC_GPLL14_OUT_EVEN 4
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#define GCC_GPLL4 5
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#define GCC_GPLL5 6
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#define GCC_GPLL7 7
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#define GCC_GPLL8 8
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#define GCC_GPLL9 9
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#define GCC_AGGRE_NOC_PCIE_3A_WEST_SF_AXI_CLK 10
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#define GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK 11
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#define GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK 12
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#define GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK 13
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#define GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK 14
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#define GCC_AGGRE_UFS_PHY_AXI_CLK 15
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#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 16
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#define GCC_AGGRE_USB2_PRIM_AXI_CLK 17
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#define GCC_AGGRE_USB3_MP_AXI_CLK 18
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#define GCC_AGGRE_USB3_PRIM_AXI_CLK 19
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#define GCC_AGGRE_USB3_SEC_AXI_CLK 20
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#define GCC_AGGRE_USB3_TERT_AXI_CLK 21
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#define GCC_AGGRE_USB4_0_AXI_CLK 22
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#define GCC_AGGRE_USB4_1_AXI_CLK 23
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#define GCC_AGGRE_USB4_2_AXI_CLK 24
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#define GCC_AV1E_AHB_CLK 25
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#define GCC_AV1E_AXI_CLK 26
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#define GCC_AV1E_XO_CLK 27
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#define GCC_BOOT_ROM_AHB_CLK 28
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#define GCC_CAMERA_AHB_CLK 29
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#define GCC_CAMERA_HF_AXI_CLK 30
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#define GCC_CAMERA_SF_AXI_CLK 31
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#define GCC_CAMERA_XO_CLK 32
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#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 33
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#define GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK 34
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#define GCC_CFG_NOC_USB2_PRIM_AXI_CLK 35
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#define GCC_CFG_NOC_USB3_MP_AXI_CLK 36
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#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 37
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#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 38
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#define GCC_CFG_NOC_USB3_TERT_AXI_CLK 39
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#define GCC_CFG_NOC_USB_ANOC_AHB_CLK 40
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#define GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK 41
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#define GCC_DISP_AHB_CLK 42
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#define GCC_DISP_HF_AXI_CLK 43
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#define GCC_EVA_AHB_CLK 44
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#define GCC_EVA_AXI0_CLK 45
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#define GCC_EVA_AXI0C_CLK 46
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#define GCC_EVA_XO_CLK 47
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#define GCC_GP1_CLK 48
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#define GCC_GP1_CLK_SRC 49
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#define GCC_GP2_CLK 50
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#define GCC_GP2_CLK_SRC 51
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#define GCC_GP3_CLK 52
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#define GCC_GP3_CLK_SRC 53
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#define GCC_GPU_CFG_AHB_CLK 54
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#define GCC_GPU_GEMNOC_GFX_CLK 55
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#define GCC_GPU_GPLL0_CLK_SRC 56
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#define GCC_GPU_GPLL0_DIV_CLK_SRC 57
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#define GCC_PCIE_0_AUX_CLK 58
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#define GCC_PCIE_0_AUX_CLK_SRC 59
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#define GCC_PCIE_0_CFG_AHB_CLK 60
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#define GCC_PCIE_0_MSTR_AXI_CLK 61
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#define GCC_PCIE_0_PHY_RCHNG_CLK 62
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#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 63
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#define GCC_PCIE_0_PIPE_CLK 64
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#define GCC_PCIE_0_SLV_AXI_CLK 65
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#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 66
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#define GCC_PCIE_1_AUX_CLK 67
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#define GCC_PCIE_1_AUX_CLK_SRC 68
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#define GCC_PCIE_1_CFG_AHB_CLK 69
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#define GCC_PCIE_1_MSTR_AXI_CLK 70
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#define GCC_PCIE_1_PHY_RCHNG_CLK 71
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#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 72
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#define GCC_PCIE_1_PIPE_CLK 73
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#define GCC_PCIE_1_SLV_AXI_CLK 74
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#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 75
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#define GCC_PCIE_2_AUX_CLK 76
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#define GCC_PCIE_2_AUX_CLK_SRC 77
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#define GCC_PCIE_2_CFG_AHB_CLK 78
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#define GCC_PCIE_2_MSTR_AXI_CLK 79
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#define GCC_PCIE_2_PHY_RCHNG_CLK 80
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#define GCC_PCIE_2_PHY_RCHNG_CLK_SRC 81
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#define GCC_PCIE_2_PIPE_CLK 82
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#define GCC_PCIE_2_SLV_AXI_CLK 83
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#define GCC_PCIE_2_SLV_Q2A_AXI_CLK 84
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#define GCC_PCIE_3A_AUX_CLK 85
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#define GCC_PCIE_3A_AUX_CLK_SRC 86
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#define GCC_PCIE_3A_CFG_AHB_CLK 87
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#define GCC_PCIE_3A_MSTR_AXI_CLK 88
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#define GCC_PCIE_3A_PHY_RCHNG_CLK 89
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#define GCC_PCIE_3A_PHY_RCHNG_CLK_SRC 90
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#define GCC_PCIE_3A_PIPE_CLK 91
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#define GCC_PCIE_3A_PIPE_CLK_SRC 92
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#define GCC_PCIE_3A_SLV_AXI_CLK 93
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#define GCC_PCIE_3A_SLV_Q2A_AXI_CLK 94
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#define GCC_PCIE_3B_AUX_CLK 95
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#define GCC_PCIE_3B_AUX_CLK_SRC 96
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#define GCC_PCIE_3B_CFG_AHB_CLK 97
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#define GCC_PCIE_3B_MSTR_AXI_CLK 98
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#define GCC_PCIE_3B_PHY_RCHNG_CLK 99
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#define GCC_PCIE_3B_PHY_RCHNG_CLK_SRC 100
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#define GCC_PCIE_3B_PIPE_CLK 101
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#define GCC_PCIE_3B_PIPE_CLK_SRC 102
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#define GCC_PCIE_3B_PIPE_DIV2_CLK 103
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#define GCC_PCIE_3B_PIPE_DIV_CLK_SRC 104
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#define GCC_PCIE_3B_SLV_AXI_CLK 105
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#define GCC_PCIE_3B_SLV_Q2A_AXI_CLK 106
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#define GCC_PCIE_4_AUX_CLK 107
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#define GCC_PCIE_4_AUX_CLK_SRC 108
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#define GCC_PCIE_4_CFG_AHB_CLK 109
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#define GCC_PCIE_4_MSTR_AXI_CLK 110
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#define GCC_PCIE_4_PHY_RCHNG_CLK 111
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#define GCC_PCIE_4_PHY_RCHNG_CLK_SRC 112
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#define GCC_PCIE_4_PIPE_CLK 113
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#define GCC_PCIE_4_PIPE_CLK_SRC 114
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#define GCC_PCIE_4_PIPE_DIV2_CLK 115
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#define GCC_PCIE_4_PIPE_DIV_CLK_SRC 116
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#define GCC_PCIE_4_SLV_AXI_CLK 117
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#define GCC_PCIE_4_SLV_Q2A_AXI_CLK 118
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#define GCC_PCIE_5_AUX_CLK 119
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#define GCC_PCIE_5_AUX_CLK_SRC 120
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#define GCC_PCIE_5_CFG_AHB_CLK 121
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#define GCC_PCIE_5_MSTR_AXI_CLK 122
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#define GCC_PCIE_5_PHY_RCHNG_CLK 123
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#define GCC_PCIE_5_PHY_RCHNG_CLK_SRC 124
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#define GCC_PCIE_5_PIPE_CLK 125
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#define GCC_PCIE_5_PIPE_CLK_SRC 126
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#define GCC_PCIE_5_PIPE_DIV2_CLK 127
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#define GCC_PCIE_5_PIPE_DIV_CLK_SRC 128
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#define GCC_PCIE_5_SLV_AXI_CLK 129
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#define GCC_PCIE_5_SLV_Q2A_AXI_CLK 130
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#define GCC_PCIE_6_AUX_CLK 131
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#define GCC_PCIE_6_AUX_CLK_SRC 132
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#define GCC_PCIE_6_CFG_AHB_CLK 133
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#define GCC_PCIE_6_MSTR_AXI_CLK 134
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#define GCC_PCIE_6_PHY_RCHNG_CLK 135
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#define GCC_PCIE_6_PHY_RCHNG_CLK_SRC 136
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#define GCC_PCIE_6_PIPE_CLK 137
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#define GCC_PCIE_6_PIPE_CLK_SRC 138
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#define GCC_PCIE_6_PIPE_DIV2_CLK 139
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#define GCC_PCIE_6_PIPE_DIV_CLK_SRC 140
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#define GCC_PCIE_6_SLV_AXI_CLK 141
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#define GCC_PCIE_6_SLV_Q2A_AXI_CLK 142
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#define GCC_PCIE_NOC_PWRCTL_CLK 143
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#define GCC_PCIE_NOC_QOSGEN_EXTREF_CLK 144
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#define GCC_PCIE_NOC_SF_CENTER_CLK 145
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#define GCC_PCIE_NOC_SLAVE_SF_EAST_CLK 146
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#define GCC_PCIE_NOC_SLAVE_SF_WEST_CLK 147
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#define GCC_PCIE_NOC_TSCTR_CLK 148
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#define GCC_PCIE_PHY_3A_AUX_CLK 149
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#define GCC_PCIE_PHY_3A_AUX_CLK_SRC 150
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#define GCC_PCIE_PHY_3B_AUX_CLK 151
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#define GCC_PCIE_PHY_3B_AUX_CLK_SRC 152
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#define GCC_PCIE_PHY_4_AUX_CLK 153
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#define GCC_PCIE_PHY_4_AUX_CLK_SRC 154
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#define GCC_PCIE_PHY_5_AUX_CLK 155
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#define GCC_PCIE_PHY_5_AUX_CLK_SRC 156
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#define GCC_PCIE_PHY_6_AUX_CLK 157
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#define GCC_PCIE_PHY_6_AUX_CLK_SRC 158
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#define GCC_PCIE_RSCC_CFG_AHB_CLK 159
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#define GCC_PCIE_RSCC_XO_CLK 160
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#define GCC_PDM2_CLK 161
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#define GCC_PDM2_CLK_SRC 162
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#define GCC_PDM_AHB_CLK 163
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#define GCC_PDM_XO4_CLK 164
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#define GCC_QMIP_AV1E_AHB_CLK 165
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#define GCC_QMIP_CAMERA_CMD_AHB_CLK 166
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#define GCC_QMIP_CAMERA_NRT_AHB_CLK 167
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#define GCC_QMIP_CAMERA_RT_AHB_CLK 168
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#define GCC_QMIP_GPU_AHB_CLK 169
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#define GCC_QMIP_PCIE_3A_AHB_CLK 170
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#define GCC_QMIP_PCIE_3B_AHB_CLK 171
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#define GCC_QMIP_PCIE_4_AHB_CLK 172
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#define GCC_QMIP_PCIE_5_AHB_CLK 173
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#define GCC_QMIP_PCIE_6_AHB_CLK 174
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#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 175
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#define GCC_QMIP_VIDEO_CVP_AHB_CLK 176
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#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 177
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#define GCC_QMIP_VIDEO_VCODEC1_AHB_CLK 178
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#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 179
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#define GCC_QUPV3_OOB_CORE_2X_CLK 180
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#define GCC_QUPV3_OOB_CORE_CLK 181
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#define GCC_QUPV3_OOB_M_AHB_CLK 182
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#define GCC_QUPV3_OOB_QSPI_S0_CLK 183
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#define GCC_QUPV3_OOB_QSPI_S0_CLK_SRC 184
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#define GCC_QUPV3_OOB_QSPI_S1_CLK 185
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#define GCC_QUPV3_OOB_QSPI_S1_CLK_SRC 186
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#define GCC_QUPV3_OOB_S0_CLK 187
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#define GCC_QUPV3_OOB_S0_CLK_SRC 188
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#define GCC_QUPV3_OOB_S1_CLK 189
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#define GCC_QUPV3_OOB_S1_CLK_SRC 190
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#define GCC_QUPV3_OOB_S_AHB_CLK 191
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#define GCC_QUPV3_OOB_TCXO_CLK 192
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#define GCC_QUPV3_WRAP0_CORE_2X_CLK 193
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#define GCC_QUPV3_WRAP0_CORE_CLK 194
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#define GCC_QUPV3_WRAP0_QSPI_S2_CLK 195
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#define GCC_QUPV3_WRAP0_QSPI_S2_CLK_SRC 196
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#define GCC_QUPV3_WRAP0_QSPI_S3_CLK 197
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#define GCC_QUPV3_WRAP0_QSPI_S3_CLK_SRC 198
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#define GCC_QUPV3_WRAP0_QSPI_S6_CLK 199
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#define GCC_QUPV3_WRAP0_QSPI_S6_CLK_SRC 200
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#define GCC_QUPV3_WRAP0_S0_CLK 201
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#define GCC_QUPV3_WRAP0_S0_CLK_SRC 202
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#define GCC_QUPV3_WRAP0_S1_CLK 203
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#define GCC_QUPV3_WRAP0_S1_CLK_SRC 204
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#define GCC_QUPV3_WRAP0_S2_CLK 205
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#define GCC_QUPV3_WRAP0_S2_CLK_SRC 206
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#define GCC_QUPV3_WRAP0_S3_CLK 207
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#define GCC_QUPV3_WRAP0_S3_CLK_SRC 208
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#define GCC_QUPV3_WRAP0_S4_CLK 209
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#define GCC_QUPV3_WRAP0_S4_CLK_SRC 210
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#define GCC_QUPV3_WRAP0_S5_CLK 211
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#define GCC_QUPV3_WRAP0_S5_CLK_SRC 212
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#define GCC_QUPV3_WRAP0_S6_CLK 213
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#define GCC_QUPV3_WRAP0_S6_CLK_SRC 214
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#define GCC_QUPV3_WRAP0_S7_CLK 215
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#define GCC_QUPV3_WRAP0_S7_CLK_SRC 216
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#define GCC_QUPV3_WRAP1_CORE_2X_CLK 217
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#define GCC_QUPV3_WRAP1_CORE_CLK 218
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#define GCC_QUPV3_WRAP1_QSPI_S2_CLK 219
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#define GCC_QUPV3_WRAP1_QSPI_S2_CLK_SRC 220
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#define GCC_QUPV3_WRAP1_QSPI_S3_CLK 221
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#define GCC_QUPV3_WRAP1_QSPI_S3_CLK_SRC 222
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#define GCC_QUPV3_WRAP1_QSPI_S6_CLK 223
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#define GCC_QUPV3_WRAP1_QSPI_S6_CLK_SRC 224
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#define GCC_QUPV3_WRAP1_S0_CLK 225
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#define GCC_QUPV3_WRAP1_S0_CLK_SRC 226
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#define GCC_QUPV3_WRAP1_S1_CLK 227
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#define GCC_QUPV3_WRAP1_S1_CLK_SRC 228
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#define GCC_QUPV3_WRAP1_S2_CLK 229
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#define GCC_QUPV3_WRAP1_S2_CLK_SRC 230
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#define GCC_QUPV3_WRAP1_S3_CLK 231
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#define GCC_QUPV3_WRAP1_S3_CLK_SRC 232
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#define GCC_QUPV3_WRAP1_S4_CLK 233
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#define GCC_QUPV3_WRAP1_S4_CLK_SRC 234
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#define GCC_QUPV3_WRAP1_S5_CLK 235
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#define GCC_QUPV3_WRAP1_S5_CLK_SRC 236
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#define GCC_QUPV3_WRAP1_S6_CLK 237
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#define GCC_QUPV3_WRAP1_S6_CLK_SRC 238
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#define GCC_QUPV3_WRAP1_S7_CLK 239
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#define GCC_QUPV3_WRAP1_S7_CLK_SRC 240
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#define GCC_QUPV3_WRAP2_CORE_2X_CLK 241
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#define GCC_QUPV3_WRAP2_CORE_CLK 242
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#define GCC_QUPV3_WRAP2_QSPI_S2_CLK 243
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#define GCC_QUPV3_WRAP2_QSPI_S2_CLK_SRC 244
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#define GCC_QUPV3_WRAP2_QSPI_S3_CLK 245
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#define GCC_QUPV3_WRAP2_QSPI_S3_CLK_SRC 246
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#define GCC_QUPV3_WRAP2_QSPI_S6_CLK 247
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#define GCC_QUPV3_WRAP2_QSPI_S6_CLK_SRC 248
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#define GCC_QUPV3_WRAP2_S0_CLK 249
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#define GCC_QUPV3_WRAP2_S0_CLK_SRC 250
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#define GCC_QUPV3_WRAP2_S1_CLK 251
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#define GCC_QUPV3_WRAP2_S1_CLK_SRC 252
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#define GCC_QUPV3_WRAP2_S2_CLK 253
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#define GCC_QUPV3_WRAP2_S2_CLK_SRC 254
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#define GCC_QUPV3_WRAP2_S3_CLK 255
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#define GCC_QUPV3_WRAP2_S3_CLK_SRC 256
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#define GCC_QUPV3_WRAP2_S4_CLK 257
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#define GCC_QUPV3_WRAP2_S4_CLK_SRC 258
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#define GCC_QUPV3_WRAP2_S5_CLK 259
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#define GCC_QUPV3_WRAP2_S5_CLK_SRC 260
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#define GCC_QUPV3_WRAP2_S6_CLK 261
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#define GCC_QUPV3_WRAP2_S6_CLK_SRC 262
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#define GCC_QUPV3_WRAP2_S7_CLK 263
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#define GCC_QUPV3_WRAP2_S7_CLK_SRC 264
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#define GCC_QUPV3_WRAP_0_M_AHB_CLK 265
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#define GCC_QUPV3_WRAP_0_S_AHB_CLK 266
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#define GCC_QUPV3_WRAP_1_M_AHB_CLK 267
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#define GCC_QUPV3_WRAP_1_S_AHB_CLK 268
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#define GCC_QUPV3_WRAP_2_M_AHB_CLK 269
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#define GCC_QUPV3_WRAP_2_S_AHB_CLK 270
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#define GCC_SDCC2_AHB_CLK 271
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#define GCC_SDCC2_APPS_CLK 272
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#define GCC_SDCC2_APPS_CLK_SRC 273
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#define GCC_SDCC4_AHB_CLK 274
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#define GCC_SDCC4_APPS_CLK 275
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#define GCC_SDCC4_APPS_CLK_SRC 276
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#define GCC_UFS_PHY_AHB_CLK 277
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#define GCC_UFS_PHY_AXI_CLK 278
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#define GCC_UFS_PHY_AXI_CLK_SRC 279
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#define GCC_UFS_PHY_AXI_HW_CTL_CLK 280
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#define GCC_UFS_PHY_ICE_CORE_CLK 281
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#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 282
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#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 283
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#define GCC_UFS_PHY_PHY_AUX_CLK 284
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#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 285
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#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 286
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#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 287
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#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 288
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#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 289
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#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 290
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#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 291
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#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 292
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK 293
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 294
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#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 295
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#define GCC_USB20_MASTER_CLK 296
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#define GCC_USB20_MASTER_CLK_SRC 297
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#define GCC_USB20_MOCK_UTMI_CLK 298
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#define GCC_USB20_MOCK_UTMI_CLK_SRC 299
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#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 300
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#define GCC_USB20_SLEEP_CLK 301
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#define GCC_USB30_MP_MASTER_CLK 302
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#define GCC_USB30_MP_MASTER_CLK_SRC 303
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#define GCC_USB30_MP_MOCK_UTMI_CLK 304
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#define GCC_USB30_MP_MOCK_UTMI_CLK_SRC 305
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#define GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC 306
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#define GCC_USB30_MP_SLEEP_CLK 307
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#define GCC_USB30_PRIM_MASTER_CLK 308
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#define GCC_USB30_PRIM_MASTER_CLK_SRC 309
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK 310
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 311
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#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 312
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#define GCC_USB30_PRIM_SLEEP_CLK 313
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#define GCC_USB30_SEC_MASTER_CLK 314
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#define GCC_USB30_SEC_MASTER_CLK_SRC 315
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#define GCC_USB30_SEC_MOCK_UTMI_CLK 316
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#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 317
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#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 318
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#define GCC_USB30_SEC_SLEEP_CLK 319
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#define GCC_USB30_TERT_MASTER_CLK 320
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#define GCC_USB30_TERT_MASTER_CLK_SRC 321
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#define GCC_USB30_TERT_MOCK_UTMI_CLK 322
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#define GCC_USB30_TERT_MOCK_UTMI_CLK_SRC 323
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#define GCC_USB30_TERT_MOCK_UTMI_POSTDIV_CLK_SRC 324
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#define GCC_USB30_TERT_SLEEP_CLK 325
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#define GCC_USB34_PRIM_PHY_PIPE_CLK_SRC 326
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#define GCC_USB34_SEC_PHY_PIPE_CLK_SRC 327
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#define GCC_USB34_TERT_PHY_PIPE_CLK_SRC 328
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#define GCC_USB3_MP_PHY_AUX_CLK 329
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#define GCC_USB3_MP_PHY_AUX_CLK_SRC 330
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#define GCC_USB3_MP_PHY_COM_AUX_CLK 331
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#define GCC_USB3_MP_PHY_PIPE_0_CLK 332
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#define GCC_USB3_MP_PHY_PIPE_0_CLK_SRC 333
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#define GCC_USB3_MP_PHY_PIPE_1_CLK 334
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#define GCC_USB3_MP_PHY_PIPE_1_CLK_SRC 335
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#define GCC_USB3_PRIM_PHY_AUX_CLK 336
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#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 337
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#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 338
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#define GCC_USB3_PRIM_PHY_PIPE_CLK 339
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#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 340
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#define GCC_USB3_SEC_PHY_AUX_CLK 341
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#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 342
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#define GCC_USB3_SEC_PHY_COM_AUX_CLK 343
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#define GCC_USB3_SEC_PHY_PIPE_CLK 344
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#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 345
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#define GCC_USB3_TERT_PHY_AUX_CLK 346
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#define GCC_USB3_TERT_PHY_AUX_CLK_SRC 347
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#define GCC_USB3_TERT_PHY_COM_AUX_CLK 348
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#define GCC_USB3_TERT_PHY_PIPE_CLK 349
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#define GCC_USB3_TERT_PHY_PIPE_CLK_SRC 350
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#define GCC_USB4_0_CFG_AHB_CLK 351
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#define GCC_USB4_0_DP0_CLK 352
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#define GCC_USB4_0_DP1_CLK 353
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#define GCC_USB4_0_MASTER_CLK 354
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#define GCC_USB4_0_MASTER_CLK_SRC 355
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#define GCC_USB4_0_PHY_DP0_CLK_SRC 356
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#define GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC 357
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#define GCC_USB4_0_PHY_DP1_CLK_SRC 358
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#define GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC 359
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#define GCC_USB4_0_PHY_P2RR2P_PIPE_CLK 360
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#define GCC_USB4_0_PHY_P2RR2P_PIPE_CLK_SRC 361
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#define GCC_USB4_0_PHY_PCIE_PIPE_CLK 362
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#define GCC_USB4_0_PHY_PCIE_PIPE_CLK_SRC 363
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#define GCC_USB4_0_PHY_PCIE_PIPE_MUX_CLK_SRC 364
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#define GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC 365
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#define GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC 366
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#define GCC_USB4_0_PHY_RX0_CLK 367
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#define GCC_USB4_0_PHY_RX0_CLK_SRC 368
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#define GCC_USB4_0_PHY_RX1_CLK 369
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#define GCC_USB4_0_PHY_RX1_CLK_SRC 370
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#define GCC_USB4_0_PHY_SYS_CLK_SRC 371
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#define GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC 372
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#define GCC_USB4_0_PHY_USB_PIPE_CLK 373
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#define GCC_USB4_0_SB_IF_CLK 374
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#define GCC_USB4_0_SB_IF_CLK_SRC 375
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#define GCC_USB4_0_SYS_CLK 376
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#define GCC_USB4_0_TMU_CLK 377
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#define GCC_USB4_0_TMU_CLK_SRC 378
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#define GCC_USB4_0_UC_HRR_CLK 379
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#define GCC_USB4_1_CFG_AHB_CLK 380
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#define GCC_USB4_1_DP0_CLK 381
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#define GCC_USB4_1_DP1_CLK 382
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#define GCC_USB4_1_MASTER_CLK 383
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#define GCC_USB4_1_MASTER_CLK_SRC 384
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#define GCC_USB4_1_PHY_DP0_CLK_SRC 385
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#define GCC_USB4_1_PHY_DP0_GMUX_2_CLK_SRC 386
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#define GCC_USB4_1_PHY_DP1_CLK_SRC 387
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#define GCC_USB4_1_PHY_DP1_GMUX_2_CLK_SRC 388
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#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK 389
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#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC 390
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#define GCC_USB4_1_PHY_PCIE_PIPE_CLK 391
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#define GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC 392
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#define GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC 393
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#define GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC 394
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#define GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC 395
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#define GCC_USB4_1_PHY_PLL_PIPE_CLK_SRC 396
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#define GCC_USB4_1_PHY_RX0_CLK 397
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#define GCC_USB4_1_PHY_RX0_CLK_SRC 398
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#define GCC_USB4_1_PHY_RX1_CLK 399
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#define GCC_USB4_1_PHY_RX1_CLK_SRC 400
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#define GCC_USB4_1_PHY_SYS_CLK_SRC 401
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#define GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC 402
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#define GCC_USB4_1_PHY_USB_PIPE_CLK 403
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#define GCC_USB4_1_SB_IF_CLK 404
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#define GCC_USB4_1_SB_IF_CLK_SRC 405
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#define GCC_USB4_1_SYS_CLK 406
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#define GCC_USB4_1_TMU_CLK 407
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#define GCC_USB4_1_TMU_CLK_SRC 408
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#define GCC_USB4_1_UC_HRR_CLK 409
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#define GCC_USB4_2_CFG_AHB_CLK 410
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#define GCC_USB4_2_DP0_CLK 411
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#define GCC_USB4_2_DP1_CLK 412
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#define GCC_USB4_2_MASTER_CLK 413
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#define GCC_USB4_2_MASTER_CLK_SRC 414
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#define GCC_USB4_2_PHY_DP0_CLK_SRC 415
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#define GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC 416
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#define GCC_USB4_2_PHY_DP1_CLK_SRC 417
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#define GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC 418
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#define GCC_USB4_2_PHY_P2RR2P_PIPE_CLK 419
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#define GCC_USB4_2_PHY_P2RR2P_PIPE_CLK_SRC 420
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#define GCC_USB4_2_PHY_PCIE_PIPE_CLK 421
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#define GCC_USB4_2_PHY_PCIE_PIPE_CLK_SRC 422
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#define GCC_USB4_2_PHY_PCIE_PIPE_MUX_CLK_SRC 423
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#define GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC 424
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#define GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC 425
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#define GCC_USB4_2_PHY_RX0_CLK 426
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#define GCC_USB4_2_PHY_RX0_CLK_SRC 427
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#define GCC_USB4_2_PHY_RX1_CLK 428
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#define GCC_USB4_2_PHY_RX1_CLK_SRC 429
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#define GCC_USB4_2_PHY_SYS_CLK_SRC 430
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#define GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC 431
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#define GCC_USB4_2_PHY_USB_PIPE_CLK 432
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#define GCC_USB4_2_SB_IF_CLK 433
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#define GCC_USB4_2_SB_IF_CLK_SRC 434
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#define GCC_USB4_2_SYS_CLK 435
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#define GCC_USB4_2_TMU_CLK 436
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#define GCC_USB4_2_TMU_CLK_SRC 437
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#define GCC_USB4_2_UC_HRR_CLK 438
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#define GCC_VIDEO_AHB_CLK 439
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#define GCC_VIDEO_AXI0_CLK 440
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#define GCC_VIDEO_AXI0C_CLK 441
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#define GCC_VIDEO_AXI1_CLK 442
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#define GCC_VIDEO_XO_CLK 443
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/* GCC power domains */
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#define GCC_PCIE_0_TUNNEL_GDSC 0
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#define GCC_PCIE_1_TUNNEL_GDSC 1
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#define GCC_PCIE_2_TUNNEL_GDSC 2
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#define GCC_PCIE_3A_GDSC 3
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#define GCC_PCIE_3A_PHY_GDSC 4
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#define GCC_PCIE_3B_GDSC 5
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#define GCC_PCIE_3B_PHY_GDSC 6
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#define GCC_PCIE_4_GDSC 7
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#define GCC_PCIE_4_PHY_GDSC 8
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#define GCC_PCIE_5_GDSC 9
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#define GCC_PCIE_5_PHY_GDSC 10
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#define GCC_PCIE_6_GDSC 11
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#define GCC_PCIE_6_PHY_GDSC 12
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#define GCC_UFS_PHY_GDSC 13
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#define GCC_USB20_PRIM_GDSC 14
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#define GCC_USB30_MP_GDSC 15
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#define GCC_USB30_PRIM_GDSC 16
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#define GCC_USB30_SEC_GDSC 17
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#define GCC_USB30_TERT_GDSC 18
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#define GCC_USB3_MP_SS0_PHY_GDSC 19
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#define GCC_USB3_MP_SS1_PHY_GDSC 20
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#define GCC_USB4_0_GDSC 21
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#define GCC_USB4_1_GDSC 22
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#define GCC_USB4_2_GDSC 23
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#define GCC_USB_0_PHY_GDSC 24
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#define GCC_USB_1_PHY_GDSC 25
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#define GCC_USB_2_PHY_GDSC 26
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/* GCC resets */
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#define GCC_AV1E_BCR 0
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#define GCC_CAMERA_BCR 1
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#define GCC_DISPLAY_BCR 2
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#define GCC_EVA_BCR 3
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#define GCC_GPU_BCR 4
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#define GCC_PCIE_0_LINK_DOWN_BCR 5
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#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 6
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#define GCC_PCIE_0_PHY_BCR 7
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#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 8
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#define GCC_PCIE_0_TUNNEL_BCR 9
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#define GCC_PCIE_1_LINK_DOWN_BCR 10
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#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 11
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#define GCC_PCIE_1_PHY_BCR 12
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#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 13
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#define GCC_PCIE_1_TUNNEL_BCR 14
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#define GCC_PCIE_2_LINK_DOWN_BCR 15
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#define GCC_PCIE_2_NOCSR_COM_PHY_BCR 16
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#define GCC_PCIE_2_PHY_BCR 17
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#define GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR 18
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#define GCC_PCIE_2_TUNNEL_BCR 19
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#define GCC_PCIE_3A_BCR 20
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#define GCC_PCIE_3A_LINK_DOWN_BCR 21
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#define GCC_PCIE_3A_NOCSR_COM_PHY_BCR 22
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#define GCC_PCIE_3A_PHY_BCR 23
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#define GCC_PCIE_3A_PHY_NOCSR_COM_PHY_BCR 24
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#define GCC_PCIE_3B_BCR 25
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#define GCC_PCIE_3B_LINK_DOWN_BCR 26
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#define GCC_PCIE_3B_NOCSR_COM_PHY_BCR 27
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#define GCC_PCIE_3B_PHY_BCR 28
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#define GCC_PCIE_3B_PHY_NOCSR_COM_PHY_BCR 29
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#define GCC_PCIE_4_BCR 30
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#define GCC_PCIE_4_LINK_DOWN_BCR 31
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#define GCC_PCIE_4_NOCSR_COM_PHY_BCR 32
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#define GCC_PCIE_4_PHY_BCR 33
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#define GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR 34
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#define GCC_PCIE_5_BCR 35
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#define GCC_PCIE_5_LINK_DOWN_BCR 36
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#define GCC_PCIE_5_NOCSR_COM_PHY_BCR 37
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#define GCC_PCIE_5_PHY_BCR 38
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#define GCC_PCIE_5_PHY_NOCSR_COM_PHY_BCR 39
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#define GCC_PCIE_6_BCR 40
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#define GCC_PCIE_6_LINK_DOWN_BCR 41
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#define GCC_PCIE_6_NOCSR_COM_PHY_BCR 42
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#define GCC_PCIE_6_PHY_BCR 43
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|
#define GCC_PCIE_6_PHY_NOCSR_COM_PHY_BCR 44
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|
#define GCC_PCIE_NOC_BCR 45
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|
#define GCC_PCIE_PHY_BCR 46
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#define GCC_PCIE_PHY_CFG_AHB_BCR 47
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#define GCC_PCIE_PHY_COM_BCR 48
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|
#define GCC_PCIE_RSCC_BCR 49
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|
#define GCC_PDM_BCR 50
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#define GCC_QUPV3_WRAPPER_0_BCR 51
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#define GCC_QUPV3_WRAPPER_1_BCR 52
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#define GCC_QUPV3_WRAPPER_2_BCR 53
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#define GCC_QUPV3_WRAPPER_OOB_BCR 54
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#define GCC_QUSB2PHY_HS0_MP_BCR 55
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#define GCC_QUSB2PHY_HS1_MP_BCR 56
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#define GCC_QUSB2PHY_PRIM_BCR 57
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#define GCC_QUSB2PHY_SEC_BCR 58
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#define GCC_QUSB2PHY_TERT_BCR 59
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#define GCC_QUSB2PHY_USB20_HS_BCR 60
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|
#define GCC_SDCC2_BCR 61
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|
#define GCC_SDCC4_BCR 62
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|
#define GCC_TCSR_PCIE_BCR 63
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#define GCC_UFS_PHY_BCR 64
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|
#define GCC_USB20_PRIM_BCR 65
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#define GCC_USB30_MP_BCR 66
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#define GCC_USB30_PRIM_BCR 67
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#define GCC_USB30_SEC_BCR 68
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#define GCC_USB30_TERT_BCR 69
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|
#define GCC_USB3_MP_SS0_PHY_BCR 70
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#define GCC_USB3_MP_SS1_PHY_BCR 71
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#define GCC_USB3_PHY_PRIM_BCR 72
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#define GCC_USB3_PHY_SEC_BCR 73
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#define GCC_USB3_PHY_TERT_BCR 74
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#define GCC_USB3_UNIPHY_MP0_BCR 75
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|
#define GCC_USB3_UNIPHY_MP1_BCR 76
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#define GCC_USB3PHY_PHY_PRIM_BCR 77
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|
#define GCC_USB3PHY_PHY_SEC_BCR 78
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|
#define GCC_USB3PHY_PHY_TERT_BCR 79
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|
#define GCC_USB3UNIPHY_PHY_MP0_BCR 80
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|
#define GCC_USB3UNIPHY_PHY_MP1_BCR 81
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|
#define GCC_USB4_0_BCR 82
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|
#define GCC_USB4_0_DP0_PHY_PRIM_BCR 83
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|
#define GCC_USB4_1_BCR 84
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|
#define GCC_USB4_2_BCR 85
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|
#define GCC_USB_0_PHY_BCR 86
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|
#define GCC_USB_1_PHY_BCR 87
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|
#define GCC_USB_2_PHY_BCR 88
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|
#define GCC_VIDEO_AXI0_CLK_ARES 89
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#define GCC_VIDEO_AXI1_CLK_ARES 90
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#define GCC_VIDEO_BCR 91
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#endif
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