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The CMN PLL controller provides clocks to networking hardware blocks and to GCC on Qualcomm IPQ9574 SoC. It receives input clock from the on-chip Wi-Fi, and produces output clocks at fixed rates. These output rates are predetermined, and are unrelated to the input clock rate. The primary purpose of CMN PLL is to supply clocks to the networking hardware such as PPE (packet process engine), PCS and the externally connected switch or PHY device. The CMN PLL block also outputs fixed rate clocks to GCC, such as 24 MHZ as XO clock and 32 KHZ as sleep clock supplied to GCC. Signed-off-by: Luo Jie <quic_luoj@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250103-qcom_ipq_cmnpll-v8-1-c89fb4d4849d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
78 lines
2.2 KiB
YAML
78 lines
2.2 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm CMN PLL Clock Controller on IPQ SoC
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Luo Jie <quic_luoj@quicinc.com>
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description:
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The CMN (or common) PLL clock controller expects a reference
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input clock. This reference clock is from the on-board Wi-Fi.
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The CMN PLL supplies a number of fixed rate output clocks to
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the devices providing networking functions and to GCC. These
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networking hardware include PPE (packet process engine), PCS
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and the externally connected switch or PHY devices. The CMN
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PLL block also outputs fixed rate clocks to GCC. The PLL's
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primary function is to enable fixed rate output clocks for
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networking hardware functions used with the IPQ SoC.
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properties:
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compatible:
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enum:
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- qcom,ipq9574-cmn-pll
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reg:
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maxItems: 1
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clocks:
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items:
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- description: The reference clock. The supported clock rates include
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25000000, 31250000, 40000000, 48000000, 50000000 and 96000000 HZ.
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- description: The AHB clock
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- description: The SYS clock
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description:
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The reference clock is the source clock of CMN PLL, which is from the
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Wi-Fi. The AHB and SYS clocks must be enabled to access CMN PLL
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clock registers.
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clock-names:
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items:
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- const: ref
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- const: ahb
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- const: sys
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"#clock-cells":
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- "#clock-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
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#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
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cmn_pll: clock-controller@9b000 {
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compatible = "qcom,ipq9574-cmn-pll";
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reg = <0x0009b000 0x800>;
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clocks = <&cmn_pll_ref_clk>,
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<&gcc GCC_CMN_12GPLL_AHB_CLK>,
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<&gcc GCC_CMN_12GPLL_SYS_CLK>;
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clock-names = "ref", "ahb", "sys";
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#clock-cells = <1>;
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assigned-clocks = <&cmn_pll CMN_PLL_CLK>;
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assigned-clock-rates-u64 = /bits/ 64 <12000000000>;
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};
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...
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