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For more than a year all emails to Bhupesh Sharma's Linaro emails bounce and there were no updates to mailmap. No reviews from Bhupesh, either, so change the maintainer to Bjorn and Konrad (Qualcomm SoC maintainers). Cc: Bhupesh Sharma <bhupesh.linux@gmail.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Konrad Dybcio <konradybcio@kernel.org> Message-ID: <20241130094758.15553-1-krzysztof.kozlowski@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
272 lines
6.7 KiB
YAML
272 lines
6.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SDHCI controller (sdhci-msm)
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Konrad Dybcio <konradybcio@kernel.org>
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description:
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Secure Digital Host Controller Interface (SDHCI) present on
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Qualcomm SOCs supports SD/MMC/SDIO devices.
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properties:
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compatible:
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oneOf:
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- enum:
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- qcom,sdhci-msm-v4
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deprecated: true
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- items:
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- enum:
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- qcom,apq8084-sdhci
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- qcom,ipq4019-sdhci
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- qcom,ipq8074-sdhci
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- qcom,msm8226-sdhci
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- qcom,msm8953-sdhci
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- qcom,msm8974-sdhci
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- qcom,msm8976-sdhci
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- qcom,msm8916-sdhci
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- qcom,msm8992-sdhci
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- qcom,msm8994-sdhci
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- qcom,msm8996-sdhci
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- qcom,msm8998-sdhci
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- const: qcom,sdhci-msm-v4 # for sdcc versions less than 5.0
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- items:
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- enum:
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- qcom,ipq5018-sdhci
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- qcom,ipq5332-sdhci
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- qcom,ipq5424-sdhci
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- qcom,ipq6018-sdhci
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- qcom,ipq9574-sdhci
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- qcom,qcm2290-sdhci
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- qcom,qcs404-sdhci
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- qcom,qcs615-sdhci
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- qcom,qdu1000-sdhci
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- qcom,sar2130p-sdhci
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- qcom,sc7180-sdhci
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- qcom,sc7280-sdhci
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- qcom,sc8280xp-sdhci
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- qcom,sdm630-sdhci
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- qcom,sdm670-sdhci
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- qcom,sdm845-sdhci
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- qcom,sdx55-sdhci
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- qcom,sdx65-sdhci
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- qcom,sdx75-sdhci
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- qcom,sm6115-sdhci
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- qcom,sm6125-sdhci
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- qcom,sm6350-sdhci
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- qcom,sm6375-sdhci
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- qcom,sm8150-sdhci
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- qcom,sm8250-sdhci
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- qcom,sm8350-sdhci
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- qcom,sm8450-sdhci
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- qcom,sm8550-sdhci
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- qcom,sm8650-sdhci
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- qcom,x1e80100-sdhci
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- const: qcom,sdhci-msm-v5 # for sdcc version 5.0
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reg:
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minItems: 1
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maxItems: 4
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reg-names:
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minItems: 1
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maxItems: 4
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clocks:
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minItems: 2
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items:
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- description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock
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- description: SDC MMC clock, MCLK
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- description: TCXO clock
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- description: clock for Inline Crypto Engine
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- description: SDCC bus voter clock
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- description: reference clock for RCLK delay calibration
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- description: sleep clock for RCLK delay calibration
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clock-names:
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minItems: 2
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items:
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- const: iface
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- const: core
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- const: xo
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- enum: [ice, bus, cal, sleep]
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- enum: [ice, bus, cal, sleep]
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- enum: [ice, bus, cal, sleep]
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- enum: [ice, bus, cal, sleep]
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dma-coherent: true
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interrupts:
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maxItems: 2
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interrupt-names:
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items:
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- const: hc_irq
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- const: pwr_irq
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pinctrl-names:
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minItems: 1
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items:
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- const: default
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- const: sleep
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pinctrl-0:
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description:
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Should specify pin control groups used for this controller.
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pinctrl-1:
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description:
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Should specify sleep pin control groups used for this controller.
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resets:
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maxItems: 1
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qcom,ddr-config:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: platform specific settings for DDR_CONFIG reg.
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qcom,dll-config:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: platform specific settings for DLL_CONFIG reg.
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iommus:
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minItems: 1
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maxItems: 8
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description: |
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phandle to apps_smmu node with sid mask.
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interconnects:
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minItems: 1
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items:
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- description: data path, sdhc to ddr
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- description: config path, cpu to sdhc
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interconnect-names:
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minItems: 1
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items:
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- const: sdhc-ddr
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- const: cpu-sdhc
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power-domains:
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description: A phandle to sdhci power domain node
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maxItems: 1
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operating-points-v2: true
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patternProperties:
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'^opp-table(-[a-z0-9]+)?$':
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if:
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properties:
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compatible:
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const: operating-points-v2
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then:
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patternProperties:
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'^opp-?[0-9]+$':
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required:
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- required-opps
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- interrupts
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allOf:
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- $ref: sdhci-common.yaml#
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sdhci-msm-v4
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then:
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properties:
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reg:
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minItems: 2
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items:
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- description: Host controller register map
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- description: SD Core register map
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- description: CQE register map
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- description: Inline Crypto Engine register map
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reg-names:
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minItems: 2
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items:
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- const: hc
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- const: core
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- const: cqhci
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- const: ice
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else:
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properties:
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reg:
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minItems: 1
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items:
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- description: Host controller register map
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- description: CQE register map
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- description: Inline Crypto Engine register map
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reg-names:
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minItems: 1
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items:
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- const: hc
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- const: cqhci
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- const: ice
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-sm8250.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/power/qcom,rpmhpd.h>
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sdhc_2: mmc@8804000 {
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compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
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reg = <0 0x08804000 0 0x1000>;
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interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC2_AHB_CLK>,
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<&gcc GCC_SDCC2_APPS_CLK>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "iface", "core", "xo";
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iommus = <&apps_smmu 0x4a0 0x0>;
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qcom,dll-config = <0x0007642c>;
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qcom,ddr-config = <0x80040868>;
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power-domains = <&rpmhpd RPMHPD_CX>;
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operating-points-v2 = <&sdhc2_opp_table>;
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sdhc2_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-19200000 {
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opp-hz = /bits/ 64 <19200000>;
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required-opps = <&rpmhpd_opp_min_svs>;
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};
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opp-50000000 {
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opp-hz = /bits/ 64 <50000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-100000000 {
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opp-hz = /bits/ 64 <100000000>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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opp-202000000 {
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opp-hz = /bits/ 64 <202000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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};
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};
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