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The Xilinx Versal premium series has CPM5 block which supports two typeA Root Port controller functionality at Gen5 speed. Add compatible string to distinguish between two CPM5 rootport controller1. since Legacy and error interrupt register and bits for both the controllers are at different offsets. Link: https://lore.kernel.org/r/20240922061318.2653503-2-thippesw@amd.com Signed-off-by: Thippeswamy Havalige <thippesw@amd.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
139 lines
4.5 KiB
YAML
139 lines
4.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: CPM Host Controller device tree for Xilinx Versal SoCs
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maintainers:
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- Bharat Kumar Gogada <bharat.kumar.gogada@amd.com>
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allOf:
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- $ref: /schemas/pci/pci-host-bridge.yaml#
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properties:
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compatible:
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enum:
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- xlnx,versal-cpm-host-1.00
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- xlnx,versal-cpm5-host
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- xlnx,versal-cpm5-host1
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reg:
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items:
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- description: CPM system level control and status registers.
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- description: Configuration space region and bridge registers.
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- description: CPM5 control and status registers.
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minItems: 2
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reg-names:
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items:
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- const: cpm_slcr
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- const: cfg
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- const: cpm_csr
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minItems: 2
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interrupts:
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maxItems: 1
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msi-map:
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description:
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Maps a Requester ID to an MSI controller and associated MSI sideband data.
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ranges:
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maxItems: 2
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"#interrupt-cells":
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const: 1
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interrupt-controller:
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description: Interrupt controller node for handling legacy PCI interrupts.
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type: object
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additionalProperties: false
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properties:
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"#address-cells":
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const: 0
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"#interrupt-cells":
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const: 1
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interrupt-controller: true
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required:
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- reg
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- reg-names
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- "#interrupt-cells"
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- interrupts
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- interrupt-map
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- interrupt-map-mask
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- bus-range
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- msi-map
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- interrupt-controller
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unevaluatedProperties: false
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examples:
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- |
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versal {
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#address-cells = <2>;
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#size-cells = <2>;
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cpm_pcie: pcie@fca10000 {
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compatible = "xlnx,versal-cpm-host-1.00";
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device_type = "pci";
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#address-cells = <3>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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interrupts = <0 72 4>;
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interrupt-parent = <&gic>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
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<0 0 0 2 &pcie_intc_0 1>,
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<0 0 0 3 &pcie_intc_0 2>,
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<0 0 0 4 &pcie_intc_0 3>;
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bus-range = <0x00 0xff>;
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ranges = <0x02000000 0x0 0xe0010000 0x0 0xe0010000 0x0 0x10000000>,
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<0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
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msi-map = <0x0 &its_gic 0x0 0x10000>;
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reg = <0x0 0xfca10000 0x0 0x1000>,
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<0x6 0x00000000 0x0 0x10000000>;
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reg-names = "cpm_slcr", "cfg";
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pcie_intc_0: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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cpm5_pcie: pcie@fcdd0000 {
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compatible = "xlnx,versal-cpm5-host";
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device_type = "pci";
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#address-cells = <3>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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interrupts = <0 72 4>;
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interrupt-parent = <&gic>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc_1 0>,
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<0 0 0 2 &pcie_intc_1 1>,
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<0 0 0 3 &pcie_intc_1 2>,
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<0 0 0 4 &pcie_intc_1 3>;
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bus-range = <0x00 0xff>;
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ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
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<0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
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msi-map = <0x0 &its_gic 0x0 0x10000>;
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reg = <0x00 0xfcdd0000 0x00 0x1000>,
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<0x06 0x00000000 0x00 0x1000000>,
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<0x00 0xfce20000 0x00 0x1000000>;
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reg-names = "cpm_slcr", "cfg", "cpm_csr";
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pcie_intc_1: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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};
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