George Shen 79a57f9479 drm/amd/display: Add 6bpc RGB case for dcn32 output bpp calculations ...

[Why]
Current DCN32 calculation doesn't consider RGB 6bpc for the DP case.
This results in an invalid output bpp being calculated when DSC is not
enabled in the configuration, failing the mode validation.

[How]
Add special case to handle 6bpc RGB in the output bpp calculation.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2025-01-06 14:44:28 -05:00

..

dcn32_fpu.c

drm/amd/display: Remove old comments

2024-07-23 17:38:29 -04:00

dcn32_fpu.h

drm/amd/display: For FPO + Vactive check that all pipes support VA

2024-04-30 09:56:50 -04:00

display_mode_vba_32.c

drm/amd/display: Account for cursor prefetch BW in DML1 mode support

2024-07-01 16:10:35 -04:00

display_mode_vba_32.h

drm/amd/display: Apply 60us prefetch for DCFCLK <= 300Mhz

2023-06-09 10:44:08 -04:00

display_mode_vba_util_32.c

drm/amd/display: Add 6bpc RGB case for dcn32 output bpp calculations

2025-01-06 14:44:28 -05:00

display_mode_vba_util_32.h

drm/amd/display: For prefetch mode > 0, extend prefetch if possible

2023-12-13 15:09:54 -05:00

display_rq_dlg_calc_32.c

drm/amd/display: Fix a test dml32_rq_dlg_get_rq_reg()

2023-06-09 09:20:40 -04:00

display_rq_dlg_calc_32.h

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