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21d07f5fdc
- Configure the HW engines to work with MSI-X - Program the LRC to use memirq infra (similar to VF) - CS_INT_VEC field added to the LRC Bspec: 60342, 72547 Signed-off-by: Ilia Levi <ilia.levi@intel.com> Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241213072538.6823-3-ilia.levi@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
38 lines
1.2 KiB
C
38 lines
1.2 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef _XE_LRC_LAYOUT_H_
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#define _XE_LRC_LAYOUT_H_
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#define CTX_CONTEXT_CONTROL (0x02 + 1)
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#define CTX_RING_HEAD (0x04 + 1)
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#define CTX_RING_TAIL (0x06 + 1)
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#define CTX_RING_START (0x08 + 1)
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#define CTX_RING_CTL (0x0a + 1)
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#define CTX_TIMESTAMP (0x22 + 1)
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#define CTX_INDIRECT_RING_STATE (0x26 + 1)
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#define CTX_PDP0_UDW (0x30 + 1)
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#define CTX_PDP0_LDW (0x32 + 1)
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#define CTX_LRM_INT_MASK_ENABLE 0x50
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#define CTX_INT_MASK_ENABLE_REG (CTX_LRM_INT_MASK_ENABLE + 1)
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#define CTX_INT_MASK_ENABLE_PTR (CTX_LRM_INT_MASK_ENABLE + 2)
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#define CTX_LRI_INT_REPORT_PTR 0x55
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#define CTX_INT_STATUS_REPORT_REG (CTX_LRI_INT_REPORT_PTR + 1)
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#define CTX_INT_STATUS_REPORT_PTR (CTX_LRI_INT_REPORT_PTR + 2)
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#define CTX_INT_SRC_REPORT_REG (CTX_LRI_INT_REPORT_PTR + 3)
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#define CTX_INT_SRC_REPORT_PTR (CTX_LRI_INT_REPORT_PTR + 4)
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#define CTX_CS_INT_VEC_REG 0x5a
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#define CTX_CS_INT_VEC_DATA (CTX_CS_INT_VEC_REG + 1)
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#define INDIRECT_CTX_RING_HEAD (0x02 + 1)
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#define INDIRECT_CTX_RING_TAIL (0x04 + 1)
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#define INDIRECT_CTX_RING_START (0x06 + 1)
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#define INDIRECT_CTX_RING_START_UDW (0x08 + 1)
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#define INDIRECT_CTX_RING_CTL (0x0a + 1)
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#endif
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