mirror of
https://github.com/torvalds/linux.git
synced 2026-04-21 16:23:59 -04:00
Pull drm updates from Dave Airlie:
"There are two external interactions of note, the msm tree pull in some
opp tree, hopefully the opp tree arrives from the same git tree
however it normally does.
There is also a new cgroup controller for device memory, that is used
by drm, so is merging through my tree. This will hopefully help open
up gpu cgroup usage a bit more and move us forward.
There is a new accelerator driver for the AMD XDNA Ryzen AI NPUs.
Then the usual xe/amdgpu/i915/msm leaders and lots of changes and
refactors across the board:
core:
- device memory cgroup controller added
- Remove driver date from drm_driver
- Add drm_printer based hex dumper
- drm memory stats docs update
- scheduler documentation improvements
new driver:
- amdxdna - Ryzen AI NPU support
connector:
- add a mutex to protect ELD
- make connector setup two-step
panels:
- Introduce backlight quirks infrastructure
- New panels: KDB KD116N2130B12, Tianma TM070JDHG34-00,
- Multi-Inno Technology MI1010Z1T-1CP11
bridge:
- ti-sn65dsi83: Add ti,lvds-vod-swing optional properties
- Provide default implementation of atomic_check for HDMI bridges
- it605: HDCP improvements, MCCS Support
xe:
- make OA buffer size configurable
- GuC capture fixes
- add ufence and g2h flushes
- restore system memory GGTT mappings
- ioctl fixes
- SRIOV PF scheduling priority
- allow fault injection
- lots of improvements/refactors
- Enable GuC's WA_DUAL_QUEUE for newer platforms
- IRQ related fixes and improvements
i915:
- More accurate engine busyness metrics with GuC submission
- Ensure partial BO segment offset never exceeds allowed max
- Flush GuC CT receive tasklet during reset preparation
- Some DG2 refactor to fix DG2 bugs when operating with certain CPUs
- Fix DG1 power gate sequence
- Enabling uncompressed 128b/132b UHBR SST
- Handle hdmi connector init failures, and no HDMI/DP cases
- More robust engine resets on Haswell and older
i915/xe display:
- HDCP fixes for Xe3Lpd
- New GSC FW ARL-H/ARL-U
- support 3 VDSC engines 12 slices
- MBUS joining sanitisation
- reconcile i915/xe display power mgmt
- Xe3Lpd fixes
- UHBR rates for Thunderbolt
amdgpu:
- DRM panic support
- track BO memory stats at runtime
- Fix max surface handling in DC
- Cleaner shader support for gfx10.3 dGPUs
- fix drm buddy trim handling
- SDMA engine reset updates
- Fix doorbell ttm cleanup
- RAS updates
- ISP updates
- SDMA queue reset support
- Rework DPM powergating interfaces
- Documentation updates and cleanups
- DCN 3.5 updates
- Use a pm notifier to more gracefully handle VRAM eviction on
suspend or hibernate
- Add debugfs interfaces for forcing scheduling to specific engine
instances
- GG 9.5 updates
- IH 4.4 updates
- Make missing optional firmware less noisy
- PSP 13.x updates
- SMU 13.x updates
- VCN 5.x updates
- JPEG 5.x updates
- GC 12.x updates
- DC FAMS updates
amdkfd:
- GG 9.5 updates
- Logging improvements
- Shader debugger fixes
- Trap handler cleanup
- Cleanup includes
- Eviction fence wq fix
msm:
- MDSS:
- properly described UBWC registers
- added SM6150 (aka QCS615) support
- DPU:
- added SM6150 (aka QCS615) support
- enabled wide planes if virtual planes are enabled (by using two
SSPPs for a single plane)
- added CWB hardware blocks support
- DSI:
- added SM6150 (aka QCS615) support
- GPU:
- Print GMU core fw version
- GMU bandwidth voting for a740 and a750
- Expose uche trap base via uapi
- UAPI error reporting
rcar-du:
- Add r8a779h0 Support
ivpu:
- Fix qemu crash when using passthrough
nouveau:
- expose GSP-RM logging buffers via debugfs
panfrost:
- Add MT8188 Mali-G57 MC3 support
rockchip:
- Gamma LUT support
hisilicon:
- new HIBMC support
virtio-gpu:
- convert to helpers
- add prime support for scanout buffers
v3d:
- Add DRM_IOCTL_V3D_PERFMON_SET_GLOBAL
vc4:
- Add support for BCM2712
vkms:
- line-per-line compositing algorithm to improve performance
zynqmp:
- Add DP audio support
mediatek:
- dp: Add sdp path reset
- dp: Support flexible length of DP calibration data
etnaviv:
- add fdinfo memory support
- add explicit reset handling"
* tag 'drm-next-2025-01-17' of https://gitlab.freedesktop.org/drm/kernel: (1070 commits)
drm/bridge: fix documentation for the hdmi_audio_prepare() callback
doc/cgroup: Fix title underline length
drm/doc: Include new drm-compute documentation
cgroup/dmem: Fix parameters documentation
cgroup/dmem: Select PAGE_COUNTER
kernel/cgroup: Remove the unused variable climit
drm/display: hdmi: Do not read EDID on disconnected connectors
drm/tests: hdmi: Add connector disablement test
drm/connector: hdmi: Do atomic check when necessary
drm/amd/display: 3.2.316
drm/amd/display: avoid reset DTBCLK at clock init
drm/amd/display: improve dpia pre-train
drm/amd/display: Apply DML21 Patches
drm/amd/display: Use HW lock mgr for PSR1
drm/amd/display: Revised for Replay Pseudo vblank control
drm/amd/display: Add a new flag for replay low hz
drm/amd/display: Remove unused read_ono_state function from Hwss module
drm/amd/display: Do not elevate mem_type change to full update
drm/amd/display: Do not wait for PSR disable on vbl enable
drm/amd/display: Remove unnecessary eDP power down
...
125 lines
3.4 KiB
C
125 lines
3.4 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#ifndef _XE_GT_H_
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#define _XE_GT_H_
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#include <linux/fault-inject.h>
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#include <drm/drm_util.h>
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#include "xe_device.h"
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#include "xe_device_types.h"
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#include "xe_hw_engine.h"
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#define for_each_hw_engine(hwe__, gt__, id__) \
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for ((id__) = 0; (id__) < ARRAY_SIZE((gt__)->hw_engines); (id__)++) \
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for_each_if(((hwe__) = (gt__)->hw_engines + (id__)) && \
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xe_hw_engine_is_valid((hwe__)))
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#define CCS_MASK(gt) (((gt)->info.engine_mask & XE_HW_ENGINE_CCS_MASK) >> XE_HW_ENGINE_CCS0)
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extern struct fault_attr gt_reset_failure;
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static inline bool xe_fault_inject_gt_reset(void)
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{
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return should_fail(>_reset_failure, 1);
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}
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struct xe_gt *xe_gt_alloc(struct xe_tile *tile);
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int xe_gt_init_hwconfig(struct xe_gt *gt);
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int xe_gt_init_early(struct xe_gt *gt);
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int xe_gt_init(struct xe_gt *gt);
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void xe_gt_mmio_init(struct xe_gt *gt);
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void xe_gt_declare_wedged(struct xe_gt *gt);
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int xe_gt_record_default_lrcs(struct xe_gt *gt);
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/**
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* xe_gt_record_user_engines - save data related to engines available to
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* userspace
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* @gt: GT structure
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*
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* Walk the available HW engines from gt->info.engine_mask and calculate data
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* related to those engines that may be used by userspace. To be used whenever
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* available engines change in runtime (e.g. with ccs_mode) or during
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* initialization
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*/
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void xe_gt_record_user_engines(struct xe_gt *gt);
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void xe_gt_suspend_prepare(struct xe_gt *gt);
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int xe_gt_suspend(struct xe_gt *gt);
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void xe_gt_shutdown(struct xe_gt *gt);
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int xe_gt_resume(struct xe_gt *gt);
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void xe_gt_reset_async(struct xe_gt *gt);
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void xe_gt_sanitize(struct xe_gt *gt);
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int xe_gt_sanitize_freq(struct xe_gt *gt);
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void xe_gt_remove(struct xe_gt *gt);
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/**
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* xe_gt_wait_for_reset - wait for gt's async reset to finalize.
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* @gt: GT structure
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* Return:
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* %true if it waited for the work to finish execution,
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* %false if there was no scheduled reset or it was done.
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*/
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static inline bool xe_gt_wait_for_reset(struct xe_gt *gt)
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{
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return flush_work(>->reset.worker);
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}
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/**
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* xe_gt_reset - perform synchronous reset
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* @gt: GT structure
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* Return:
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* %true if it waited for the reset to finish,
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* %false if there was no scheduled reset.
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*/
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static inline bool xe_gt_reset(struct xe_gt *gt)
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{
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xe_gt_reset_async(gt);
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return xe_gt_wait_for_reset(gt);
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}
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/**
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* xe_gt_any_hw_engine_by_reset_domain - scan the list of engines and return the
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* first that matches the same reset domain as @class
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* @gt: GT structure
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* @class: hw engine class to lookup
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*/
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struct xe_hw_engine *
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xe_gt_any_hw_engine_by_reset_domain(struct xe_gt *gt, enum xe_engine_class class);
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/**
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* xe_gt_any_hw_engine - scan the list of engines and return the
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* first available
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* @gt: GT structure
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*/
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struct xe_hw_engine *xe_gt_any_hw_engine(struct xe_gt *gt);
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struct xe_hw_engine *xe_gt_hw_engine(struct xe_gt *gt,
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enum xe_engine_class class,
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u16 instance,
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bool logical);
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static inline bool xe_gt_has_indirect_ring_state(struct xe_gt *gt)
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{
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return gt->info.has_indirect_ring_state &&
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xe_device_uc_enabled(gt_to_xe(gt));
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}
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static inline bool xe_gt_is_media_type(struct xe_gt *gt)
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{
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return gt->info.type == XE_GT_TYPE_MEDIA;
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}
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static inline bool xe_gt_is_usm_hwe(struct xe_gt *gt, struct xe_hw_engine *hwe)
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{
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struct xe_device *xe = gt_to_xe(gt);
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return xe->info.has_usm && hwe->class == XE_ENGINE_CLASS_COPY &&
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hwe->instance == gt->usm.reserved_bcs_instance;
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}
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#endif
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