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0914c1e45d
Coarse Powergating is a power saving technique where Render and Media
can be power-gated independently irrespective of the rest of the GT.
For debug purposes, it is useful to expose the powergating information.
v2: move to debugfs
add details to commit message
add per-slice status for media
define reg bits in descending order (Matt Roper)
v3: fix return statement
fix kernel-doc
use loop for media slices
use helper function for status (Michal)
v4: add pg prefix
do not wake GT if in C6 (Badal)
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
Reviewed-by: Badal Nilawar <badal.nilawar@intel.com>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240906071126.28078-3-riana.tauro@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
22 lines
520 B
C
22 lines
520 B
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef _XE_GT_IDLE_H_
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#define _XE_GT_IDLE_H_
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#include "xe_gt_idle_types.h"
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struct drm_printer;
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struct xe_gt;
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int xe_gt_idle_init(struct xe_gt_idle *gtidle);
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void xe_gt_idle_enable_c6(struct xe_gt *gt);
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void xe_gt_idle_disable_c6(struct xe_gt *gt);
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void xe_gt_idle_enable_pg(struct xe_gt *gt);
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void xe_gt_idle_disable_pg(struct xe_gt *gt);
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int xe_gt_idle_pg_print(struct xe_gt *gt, struct drm_printer *p);
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#endif /* _XE_GT_IDLE_H_ */
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