mirror of
https://github.com/torvalds/linux.git
synced 2026-04-23 17:15:46 -04:00
Some shell tests compete for resources and so can't run with other tests, tag such tests. The "(exclusive)" stems from shared/exclusive to describe how the tests run as if holding a lock. For ARM/coresight tests: Suggested-by: James Clark <james.clark@linaro.org> Additional failing tests: Suggested-by: Namhyung Kim <namhyung@kernel.org> Tested-by: James Clark <james.clark@linaro.org> Signed-off-by: Ian Rogers <irogers@google.com> Cc: Colin Ian King <colin.i.king@gmail.com> Cc: Howard Chu <howardchu95@gmail.com> Cc: Weilin Wang <weilin.wang@intel.com> Cc: Ilya Leoshkevich <iii@linux.ibm.com> Cc: Thomas Richter <tmricht@linux.ibm.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Dapeng Mi <dapeng1.mi@linux.intel.com> Cc: Athira Jajeev <atrajeev@linux.vnet.ibm.com> Cc: Michael Petlan <mpetlan@redhat.com> Cc: Veronika Molnarova <vmolnaro@redhat.com> Link: https://lore.kernel.org/r/20241025192109.132482-6-irogers@google.com Signed-off-by: Namhyung Kim <namhyung@kernel.org>
23 lines
848 B
Bash
Executable File
23 lines
848 B
Bash
Executable File
#!/bin/bash
|
|
# test Intel TPEBS counting mode (exclusive)
|
|
# SPDX-License-Identifier: GPL-2.0
|
|
|
|
set -e
|
|
grep -q GenuineIntel /proc/cpuinfo || { echo Skipping non-Intel; exit 2; }
|
|
|
|
# Use this event for testing because it should exist in all platforms
|
|
event=cache-misses:R
|
|
|
|
# Hybrid platforms output like "cpu_atom/cache-misses/R", rather than as above
|
|
alt_name=/cache-misses/R
|
|
|
|
# Without this cmd option, default value or zero is returned
|
|
#echo "Testing without --record-tpebs"
|
|
#result=$(perf stat -e "$event" true 2>&1)
|
|
#[[ "$result" =~ $event || "$result" =~ $alt_name ]] || exit 1
|
|
|
|
# In platforms that do not support TPEBS, it should execute without error.
|
|
echo "Testing with --record-tpebs"
|
|
result=$(perf stat -e "$event" --record-tpebs -a sleep 0.01 2>&1)
|
|
[[ "$result" =~ "perf record" && "$result" =~ $event || "$result" =~ $alt_name ]] || exit 1
|