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This adds device tree bindings for the IXP4xx V.35 WAN high speed serial (HSS) link. An example is added to the NPE example where the HSS appears as a child. Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
101 lines
2.6 KiB
YAML
101 lines
2.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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# Copyright 2021 Linaro Ltd.
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/net/intel,ixp4xx-hss.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Intel IXP4xx V.35 WAN High Speed Serial Link (HSS)
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maintainers:
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- Linus Walleij <linus.walleij@linaro.org>
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description: |
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The Intel IXP4xx HSS makes use of the IXP4xx NPE (Network
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Processing Engine) and the IXP4xx Queue Manager to process
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V.35 Wideband Modem (WAN) links.
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properties:
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compatible:
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const: intel,ixp4xx-hss
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reg:
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maxItems: 1
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description: The HSS instance
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intel,npe-handle:
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$ref: '/schemas/types.yaml#/definitions/phandle-array'
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maxItems: 1
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description: phandle to the NPE this HSS instance is using
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and the instance to use in the second cell
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intel,queue-chl-rxtrig:
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$ref: '/schemas/types.yaml#/definitions/phandle-array'
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maxItems: 1
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description: phandle to the RX trigger queue on the NPE
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intel,queue-chl-txready:
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$ref: '/schemas/types.yaml#/definitions/phandle-array'
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maxItems: 1
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description: phandle to the TX ready queue on the NPE
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intel,queue-pkt-rx:
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$ref: '/schemas/types.yaml#/definitions/phandle-array'
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maxItems: 1
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description: phandle to the packet RX queue on the NPE
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intel,queue-pkt-tx:
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$ref: '/schemas/types.yaml#/definitions/phandle-array'
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maxItems: 4
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description: phandle to the packet TX0, TX1, TX2 and TX3 queues on the NPE
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intel,queue-pkt-rxfree:
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$ref: '/schemas/types.yaml#/definitions/phandle-array'
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maxItems: 4
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description: phandle to the packet RXFREE0, RXFREE1, RXFREE2 and
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RXFREE3 queues on the NPE
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intel,queue-pkt-txdone:
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$ref: '/schemas/types.yaml#/definitions/phandle-array'
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maxItems: 1
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description: phandle to the packet TXDONE queue on the NPE
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cts-gpios:
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maxItems: 1
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description: Clear To Send (CTS) GPIO line
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rts-gpios:
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maxItems: 1
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description: Ready To Send (RTS) GPIO line
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dcd-gpios:
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maxItems: 1
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description: Data Carrier Detect (DCD) GPIO line
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dtr-gpios:
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maxItems: 1
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description: Data Terminal Ready (DTR) GPIO line
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clk-internal-gpios:
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maxItems: 1
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description: Clock internal GPIO line, driving this high will make the HSS
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use internal clocking as opposed to external clocking
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required:
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- compatible
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- reg
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- intel,npe-handle
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- intel,queue-chl-rxtrig
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- intel,queue-chl-txready
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- intel,queue-pkt-rx
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- intel,queue-pkt-tx
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- intel,queue-pkt-rxfree
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- intel,queue-pkt-txdone
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- cts-gpios
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- rts-gpios
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- dcd-gpios
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- dtr-gpios
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- clk-internal-gpios
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additionalProperties: false
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