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There are 4 USB controllers on MT8195, the controllers (IP1~IP3, exclude IP0) have a wrong default SOF/ITP interval which is calculated from the frame counter clock 24Mhz by default, but in fact, the frame counter clock is 48Mhz, so we should set the accurate interval according to 48Mhz. Here add a new compatible for MT8195, it's also supported in driver. But the first controller (IP0) has no such issue, we prefer to use generic compatible, e.g. mt8192's compatible. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1629189389-18779-2-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
210 lines
5.7 KiB
YAML
210 lines
5.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (c) 2020 MediaTek
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/usb/mediatek,mtk-xhci.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek USB3 xHCI Device Tree Bindings
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maintainers:
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- Chunfeng Yun <chunfeng.yun@mediatek.com>
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allOf:
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- $ref: "usb-xhci.yaml"
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description: |
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There are two scenarios:
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case 1: only supports xHCI driver;
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case 2: supports dual-role mode, and the host is based on xHCI driver.
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properties:
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# common properties for both case 1 and case 2
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compatible:
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items:
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- enum:
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- mediatek,mt2701-xhci
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- mediatek,mt2712-xhci
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- mediatek,mt7622-xhci
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- mediatek,mt7623-xhci
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- mediatek,mt7629-xhci
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- mediatek,mt8173-xhci
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- mediatek,mt8183-xhci
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- mediatek,mt8192-xhci
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- mediatek,mt8195-xhci
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- const: mediatek,mtk-xhci
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reg:
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minItems: 1
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items:
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- description: the registers of xHCI MAC
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- description: the registers of IP Port Control
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reg-names:
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minItems: 1
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items:
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- const: mac
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- const: ippc # optional, only needed for case 1.
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interrupts:
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description:
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use "interrupts-extended" when the interrupts are connected to the
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separate interrupt controllers
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minItems: 1
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items:
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- description: xHCI host controller interrupt
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- description: optional, wakeup interrupt used to support runtime PM
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interrupt-names:
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items:
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- const: host
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- const: wakeup
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power-domains:
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description: A phandle to USB power domain node to control USB's MTCMOS
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maxItems: 1
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clocks:
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minItems: 1
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items:
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- description: Controller clock used by normal mode
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- description: Reference clock used by low power mode etc
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- description: Mcu bus clock for register access
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- description: DMA bus clock for data transfer
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- description: controller clock
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clock-names:
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minItems: 1
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items:
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- const: sys_ck # required, the following ones are optional
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- const: ref_ck
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- const: mcu_ck
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- const: dma_ck
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- const: xhci_ck
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assigned-clocks:
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minItems: 1
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maxItems: 5
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assigned-clock-parents:
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minItems: 1
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maxItems: 5
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phys:
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description:
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List of all PHYs used on this HCD, it's better to keep PHYs in order
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as the hardware layout
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minItems: 1
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items:
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- description: USB2/HS PHY # required, others are optional
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- description: USB3/SS(P) PHY
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- description: USB2/HS PHY
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- description: USB3/SS(P) PHY
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- description: USB2/HS PHY
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- description: USB3/SS(P) PHY
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- description: USB2/HS PHY
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- description: USB3/SS(P) PHY
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- description: USB2/HS PHY
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vusb33-supply:
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description: Regulator of USB AVDD3.3v
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vbus-supply:
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description: Regulator of USB VBUS5v
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usb3-lpm-capable: true
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usb2-lpm-disable: true
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imod-interval-ns:
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description:
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Interrupt moderation interval value, it is 8 times as much as that
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defined in the xHCI spec on MTK's controller.
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default: 5000
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# the following properties are only used for case 1
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wakeup-source:
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description: enable USB remote wakeup, see power/wakeup-source.txt
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type: boolean
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mediatek,syscon-wakeup:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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maxItems: 1
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description:
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A phandle to syscon used to access the register of the USB wakeup glue
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layer between xHCI and SPM, the field should always be 3 cells long.
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items:
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items:
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- description:
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The first cell represents a phandle to syscon
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- description:
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The second cell represents the register base address of the glue
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layer in syscon
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- description: |
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The third cell represents the hardware version of the glue layer,
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1 - used by mt8173 etc, revision 1 without following IPM rule;
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2 - used by mt2712 etc, revision 2 following IPM rule;
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101 - used by mt8183, specific 1.01;
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102 - used by mt8192, specific 1.02;
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enum: [1, 2, 101, 102]
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mediatek,u3p-dis-msk:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: The mask to disable u3ports, bit0 for u3port0,
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bit1 for u3port1, ... etc
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mediatek,u2p-dis-msk:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: The mask to disable u2ports, bit0 for u2port0,
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bit1 for u2port1, ... etc
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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patternProperties:
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"@[0-9a-f]{1}$":
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type: object
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description: The hard wired USB devices.
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dependencies:
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wakeup-source: [ 'mediatek,syscon-wakeup' ]
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mt8173-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/power/mt8173-power.h>
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usb@11270000 {
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compatible = "mediatek,mt8173-xhci", "mediatek,mtk-xhci";
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reg = <0x11270000 0x1000>, <0x11280700 0x0100>;
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reg-names = "mac", "ippc";
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
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clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
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clock-names = "sys_ck", "ref_ck";
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phys = <&u3port0 PHY_TYPE_USB3>, <&u2port1 PHY_TYPE_USB2>;
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vusb33-supply = <&mt6397_vusb_reg>;
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vbus-supply = <&usb_p1_vbus>;
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imod-interval-ns = <10000>;
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mediatek,syscon-wakeup = <&pericfg 0x400 1>;
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wakeup-source;
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usb3-lpm-capable;
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};
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...
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