Mario Limonciello 83293f7f3d drm/amd/display: reset dcn31 SMU mailbox on failures ...

Otherwise future commands may fail as well leading to downstream
problems that look like they stemmed from a timeout the first time
but really didn't.

Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2022-01-11 15:44:27 -05:00

..

dcn31_clk_mgr.c

drm/amd/display: Send s0i2_rdy in stream_count == 0 optimization

2021-12-30 08:54:44 -05:00

dcn31_clk_mgr.h

drm/amd/display: bring dcn31 clk mgr in line with other version style

2021-11-17 16:58:07 -05:00

dcn31_smu.c

drm/amd/display: reset dcn31 SMU mailbox on failures

2022-01-11 15:44:27 -05:00

dcn31_smu.h

drm/amd/display: Add DCN3.1 clock manager support

2021-06-04 16:03:26 -04:00