Niranjana Vishwanathapura 7407f2e5c3 drm/xe/pvc: Force even num engines to use 64B ...

Wa_16017236439 requires that we update BCS_SWCTRL
(via indirect context batch buffer) to set 64B
transfers when running on an even-numbered BCS
engine and 256B on an odd-numbered BCS engine.

v2: Move WA from engine_was[] to lrc_was[]

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

2023-12-21 11:40:27 -05:00

..

xe_engine_regs.h

drm/xe/pvc: Force even num engines to use 64B

2023-12-21 11:40:27 -05:00

xe_gpu_commands.h

drm/xe: Emit a render cache flush after each rcs/ccs batch

2023-12-19 18:35:21 -05:00

xe_gt_regs.h

drm/xe/xe2: Handle fused-off CCS engines

2023-12-21 11:40:25 -05:00

xe_guc_regs.h

drm/xe/xe2: Program GuC's MOCS on Xe2 and beyond

2023-12-21 11:40:26 -05:00

xe_lrc_layout.h

drm/xe: Remove dependency on intel_lrc_reg.h

2023-12-19 18:29:21 -05:00

xe_reg_defs.h

drm/xe: Rename reg field to addr

2023-12-19 18:33:50 -05:00

xe_regs.h

drm/xe: base definitions for the GSCCS

2023-12-21 11:40:20 -05:00