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d0672fa493
Added timestamp provider support for the Tegra234 in devicetree bindings. From Tegra234 SoC onwards, the nvidia,gpio-controller property is required. This is needed as the tegra always-on (AON) GPIO HTE/GTE provider depends on the AON GPIO controller where it needs to do namespace conversion between GPIO line number (belonging to AON GPIO controller instance) and the GTE slice bits. Signed-off-by: Dipen Patel <dipenp@nvidia.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
141 lines
3.7 KiB
YAML
141 lines
3.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/timestamp/nvidia,tegra194-hte.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Tegra on chip generic hardware timestamping engine (HTE) provider
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maintainers:
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- Dipen Patel <dipenp@nvidia.com>
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description:
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Tegra SoC has two instances of generic hardware timestamping engines (GTE)
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known as GTE GPIO and GTE IRQ, which can monitor subset of GPIO and on chip
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IRQ lines for the state change respectively, upon detection it will record
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timestamp (taken from system counter) in its internal hardware FIFO. It has
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a bitmap array arranged in 32bit slices where each bit represent signal/line
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to enable or disable for the hardware timestamping. The GTE GPIO monitors
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GPIO lines from the AON (always on) GPIO controller.
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properties:
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compatible:
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enum:
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- nvidia,tegra194-gte-aon
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- nvidia,tegra194-gte-lic
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- nvidia,tegra234-gte-aon
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- nvidia,tegra234-gte-lic
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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nvidia,int-threshold:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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HTE device generates its interrupt based on this u32 FIFO threshold
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value. The recommended value is 1.
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minimum: 1
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maximum: 256
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nvidia,slices:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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HTE lines are arranged in 32 bit slice where each bit represents different
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line/signal that it can enable/configure for the timestamp. It is u32
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property and the value depends on the HTE instance in the chip.
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enum: [3, 11, 17]
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nvidia,gpio-controller:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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The phandle to AON gpio controller instance. This is required to handle
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namespace conversion between GPIO and GTE.
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'#timestamp-cells':
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description:
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This represents number of line id arguments as specified by the
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consumers. For the GTE IRQ, this is IRQ number as mentioned in the
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SoC technical reference manual. For the GTE GPIO, its value is same as
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mentioned in the nvidia GPIO device tree binding document.
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const: 1
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required:
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- compatible
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- reg
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- interrupts
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- nvidia,slices
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- "#timestamp-cells"
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- nvidia,tegra194-gte-aon
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- nvidia,tegra234-gte-aon
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then:
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properties:
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nvidia,slices:
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const: 3
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- if:
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properties:
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compatible:
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contains:
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enum:
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- nvidia,tegra194-gte-lic
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then:
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properties:
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nvidia,slices:
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const: 11
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- if:
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properties:
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compatible:
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contains:
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enum:
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- nvidia,tegra234-gte-lic
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then:
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properties:
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nvidia,slices:
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const: 17
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- if:
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properties:
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compatible:
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contains:
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enum:
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- nvidia,tegra234-gte-aon
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then:
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required:
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- nvidia,gpio-controller
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additionalProperties: false
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examples:
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- |
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tegra_hte_aon: timestamp@c1e0000 {
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compatible = "nvidia,tegra194-gte-aon";
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reg = <0xc1e0000 0x10000>;
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interrupts = <0 13 0x4>;
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nvidia,int-threshold = <1>;
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nvidia,slices = <3>;
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#timestamp-cells = <1>;
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};
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- |
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tegra_hte_lic: timestamp@3aa0000 {
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compatible = "nvidia,tegra194-gte-lic";
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reg = <0x3aa0000 0x10000>;
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interrupts = <0 11 0x4>;
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nvidia,int-threshold = <1>;
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nvidia,slices = <11>;
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#timestamp-cells = <1>;
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};
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...
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